Kompendium - Datorteknik

end component;--component aluport(clk,rst : in std_logic;dbus : inout std_logic_vector(7 downto 0);styr_alu : in std_logic_vector(3 downto 0);inport : in std_logic_vector(7 downto 0);utport : out std_logic_vector(7 downto 0);cnz : out std_logic_vector(2 downto 0););end component;--component aregport(clk,rst : in std_logic;dbus : in std_logic_vector(7 downto 0);abus : out std_logic_vector(11 downto 0);cnz : in std_logic_vector(2 downto 0););end component;--component ioport(clk,rst : in std_logic;dbus : inout std_logic_vector(7 downto 0);styr : in std_logic_vector(4 downto 0););end component;--component romport (a : in std_logic_vector (11 downto 0);d : out std_logic_vector (7 downto 0);ce,oe : in std_logic;end component;-- Interna signaler i testbänkensignal clk : std_logic := ’0’;signal rst : std_logic := ’1’;signal dbus, inport,utport : std_logic_vector(7 downto 0);signal abus : std_logic_vector(11 downto 0);signal cnz : std_logic_vector(2 downto 0);signal styr_alu,styr_areg : std_logic_vector(3 downto 0);83