Kompendium - Datorteknik

u : OUT std_logic_vector(3 downto 0));END COMPONENT;SIGNAL clk : std_logic;SIGNAL rst : std_logic;SIGNAL kb : std_logic_vector(4 downto 0);SIGNAL u : std_logic_vector(3 downto 0);BEGINuut: add PORT MAP(clk => clk,rst => rst,stb => kb(4),kb => kb(3 downto 0),u => u);-- *** Test Bench - User Defined Section ***-- clk 1 Mhztb : PROCESSBEGINclk