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XN62Lxxx 1024 28 28 SRAM 0x1000 0000 0x1000 3F00 CTRL_BASE_PTR DMA (SRAM) 1GB alternate channel 20 . . . alternate channel 1 alternate channel 0 primary channel 20 . . . primary channel 1 primary channel 0 0x2A0 0x2B0 0x170 0x160 0x150 0x140 0x020 0x010 0x000 unused channel control data destination end pointer source end pointer 0x00C 0x008 0x004 0x000 Figure 19-2: DMA 19.7.5.1 src_data_end_ptr DMA 2 R DMA DMA Table 19-19: src_data_end_ptr 31:0 src_data_end_ptr 19.7.5.2 dst_data_end_ptr DMA 2 R DMA Table 19-20: dst_data_end_ptr 31:0 dst_data_end_ptr 276 www.xinnovatech.com
XN62Lxxx 19.7.5.3 DMA channel_cfg DMA 2 SRAM channel_cfg 2 R N channel_cfg SRAM src_size dst_size n_minus_1 dst_size src_size N cycle_ctrl 000 channel_cfg SRAM R SRAM . Table 19-21: channel_cfg Name 2:0 cycle_ctrl DMA 3 000: 001: / DMA 100 - 111 13:4 n_minus_1 DMA DMA DMA DMA 10 DMA 000000000 = 1 DMA 000000001 = 2 DMA 000000010 = 3 DMA 000000011 = 4 DMA 000000100 = 5 DMA ... 111111111 = 1024 DMA DMA DMA 17:14 R_power DMA 0000: DMA 0001: 2 DMA 0010: 4 DMA 0011: 8 DMA 0100: 16 DMA 0101: 32 DMA 0110: 64 DMA 0111: 128 DMA 1000: 256 DMA 1001: 512 DMA www.xinnovatech.com 277
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XN62Lxxx 32 IC ARM + xDSP , 88K
Page 3 and 4:
XN62Lxxx 2 . Flash (bytes) SRAM
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XN62Lxxx www.xinnovatech.com 5 3.2
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XN62Lxxx 3.4 Table 3-1: QFP64 QF
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XN62Lxxx QFP64 QFP48 MISO/
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XN62Lxxx QFP64 QFP48 PWM1_5
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XN62Lxxx QFP64 QFP48 PIO2_1
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XN62Lxxx CT16B1_MAT1 O PIO0_16 PIO1
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XN62Lxxx 5 5.1 ARM Cortex-M0 Cort
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XN62Lxxx Private peripheral Reserve
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XN62Lxxx 0xE000E000 ~ 0xE000E0FF 0x
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XN62Lxxx 17:12 VECTPENDING RO : 2
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XN62Lxxx Table 5-7: (CCR, 0xE000-ED
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XN62Lxxx 0~3 33 17 0x84 SPI (2) T
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XN62Lxxx 31:0 SETPEND IRQ0~IRQ31 .
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XN62Lxxx 28 PWM1 29 DMA 30 RTC 31 D
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XN62Lxxx • • • • Table
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XN62Lxxx RESET#Schmitt trigger 15
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XN62Lxxx 5 - - 0x0 6 BODINTCLR -
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XN62Lxxx 31:9 - - 0x0 5.6.2.4 20
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XN62Lxxx 12MHz 50MHz 6 100 01 () 2
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XN62Lxxx 7:0 DIV AHB 0 0x01 1: 1.
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XN62Lxxx 1 25 ADC2 ADC2 1 0 1 2
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XN62Lxxx 0x01 0x03 ~ 0xFF 1 3 ~
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XN62Lxxx 5.6.3.3 RTC RTC 32 1 kHz
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XN62Lxxx 1 31:16 - - 0 5.6.3.6 P
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XN62Lxxx 1. PCON DPDEN 0 2. ARM
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XN62Lxxx RTC XN62L • WAKEUP XN
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XN62Lxxx 3 ERPIO0_3 PIO0_3 0 0 =
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XN62Lxxx 0 SRPIO0_0 PIO0_0 0 0 = 1
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XN62Lxxx 1 DMA 11 PWM0_RST_N PWM0
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XN62Lxxx 0x3 3 3 15:13 CLK_DIV
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XN62Lxxx PIO0_7 R/W 0x064 PIO0_7/C
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XN62Lxxx 5.7.2.2 PIO0_1 IOCON Tabl
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XN62Lxxx 5.7.2.4 PIO0_3 IOCON Tabl
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XN62Lxxx 0x5 0x6 IOCONFIGCLKDIV5. I
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XN62Lxxx 0x4 0x5 0x6 IOCONFIGCLKDIV
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XN62Lxxx 0x1 0x2 0x3 0x4 0x5 0x6 IO
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XN62Lxxx 2:0 FUNC . 000 0x0 0x1 0x
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XN62Lxxx 6 INV 0 0 . 1 . 7 - . 1
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XN62Lxxx 1 . 5 - . 0 6 INV 0 0 . 1
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XN62Lxxx 0 . 1 . 5 - . 0 6 INV 0 0
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XN62Lxxx 0 . 1 . 5 - . 0 6 INV 0 0
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XN62Lxxx 0x3 0x4 0x5 CT32B0_CAP3.
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XN62Lxxx 2:0 FUNC . 000 0x0 0
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XN62Lxxx 0x6 IOCONFIGCLKDIV6. 31:16
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XN62Lxxx 0x3 3 3 15:13 CLK_DIV
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XN62Lxxx 0x0 0x1 0x2 0x3 1 1 2
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XN62Lxxx 1 12:11 S_MODE 00 0x0 0x
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XN62Lxxx 1 . 10 OD 0 0 1 12:11
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XN62Lxxx 8 - . 0 9 DRV . 0 0 1 .
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XN62Lxxx 1 8 - . 0 9 DRV . 0 0 1
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XN62Lxxx 1 . 7 - . 1 8 - . 0 9 DRV
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XN62Lxxx 5 - . 0 6 INV 0 0 . 1 .
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XN62Lxxx 4 MODE (). 1 0 . 1 . 5 -
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XN62Lxxx 0x5 PWM1_5. 3 - 0 4 MODE
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XN62Lxxx 0x2 0x3 0x4 0x5 0x6 CT32B
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XN62Lxxx 5.7.2.19 PIO2_9 IOCON Tab
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XN62Lxxx 0x3 0x4 0x5 0x6 IOCONFIGCL
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XN62Lxxx 0x1 0x2 0x3 0x4 0x5 0x6 IO
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XN62Lxxx 0x2 0x3 0x4 0x5 0x6 IOCONF
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XN62Lxxx 6 PWM 6.1 XN62L 3 PWM0P
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XN62Lxxx 6.2 PWM Table 6-1: PWM
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XN62Lxxx 6.3.1 PWM Table 6-3 PWM (
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XN62Lxxx 26 CH2OUTEN 2 0 0 1 27
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XN62Lxxx PWM 4 FTACK4 1 FFLAG40
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XN62Lxxx 4 OUT4 PWMn_4 0 0 0 1 1
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XN62Lxxx Table 6-11: PWM (DMAP1) 1
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XN62Lxxx 0 1 12 TOPNEG67 PWMn 6
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XN62Lxxx 1 1 12 FAULTVAL4 PWM FPS
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XN62Lxxx Match 0 PWMn_0 0PWMn_1
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XN62Lxxx 0 CNTR VAL5 1 CNTR VAL
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XN62Lxxx 4 3 2 Up Counter Modulus =
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XN62Lxxx PWM 0 PWM 2 PWM 4 AC Input
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XN62Lxxx Desired Load Voltage Deadt
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XN62Lxxx 4 3 2 Up/Down Counter Modu
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XN62Lxxx Up/Down Counter Reload Cha
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XN62Lxxx LDFQ[3:0] = 0000 = Reload
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XN62Lxxx Table 6-23: PWM PWMn_0 P
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XN62Lxxx 7 GPIO 7.1 XN62L 55 GPIO
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XN62Lxxx 7.3.3 GPIO 0 1 GPIO GP
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XN62Lxxx 1 . 7.3.11 GPIO lE Tab
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XN62Lxxx CAPTURE REGISTER 3 CAPTURE
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XN62Lxxx - - 0x040 - 0x06C - CTCR
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XN62Lxxx 0 5 MR1S MR1 TC TC PC T
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XN62Lxxx 0 10 CAP3FE 1 1 1 0 CR
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XN62Lxxx PCLK CAP CAP PCLK CAP
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XN62Lxxx 8.3.11.3 Primary Second
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XN62Lxxx CAPTURE REGISTER 3 CAPTURE
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XN62Lxxx 2 MR2INT 2 0 3 MR3INT 3
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XN62Lxxx 0 8 MR2S MR2 TC TC PC T
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XN62Lxxx 9.3.9 Table 9-11: (CR0
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XN62Lxxx 2:0 CTM / PCLK 00 (PC) P
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XN62Lxxx 10 (WDT) 10.1 • •
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XN62Lxxx 1 WARNINT WINDOW (WDTC)
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XN62Lxxx 0x1 WDT 0x2 0x3 . . 30:
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XN62Lxxx WDCLK / 4 Watchdog Counter
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XN62Lxxx FILTER_CR R/W 0x280 0x000
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XN62Lxxx 11.2.9 CORDIC X Table 11-
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XN62Lxxx 15:0 FILTER_RESULT . 0 16
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XN62Lxxx 2. CORDIC_X, CORDIC_Y COR
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XN62Lxxx 5. www.xinnovatech.com 20
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XN62Lxxx 12.2 Table 12-1: UART0,1
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XN62Lxxx 1 THR . 3 RBRIE RBR 0
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XN62Lxxx 12.4.2 IrDA UART IRDAEN
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XN62Lxxx CR0 R/W 0x000 0 0x0
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XN62Lxxx 15:0 DATA TNF 1 Tx FIFO
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XN62Lxxx 13.3.9 SPI 1 SPI FIFO
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XN62Lxxx Figure 13-2: SPI CPOL = 0
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XN62Lxxx CLK FS DX/DR MSB LSB 4 to
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XN62Lxxx IMSC R/W 0x014 RIS RO 0x
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XN62Lxxx 14.3.6 4 Table 14-8: (I
Page 225 and 226: XN62Lxxx CLK CS DI MSB LSB DO Q MSB
Page 227 and 228: XN62Lxxx www.xinnovatech.com 227
Page 229 and 230: XN62Lxxx 15.3 Table 15-2: ( 0x400
Page 231 and 232: XN62Lxxx TWSEN: TWS • TWS EN 1
Page 233 and 234: XN62Lxxx Table 15-11: TWS (MASK0 -
Page 235 and 236: XN62Lxxx S SLAVE ADDRESS RW=1 A DAT
Page 237 and 238: XN62Lxxx reception of the own Slave
Page 239 and 240: XN62Lxxx 15.4.6 TWS Table 15-14:
Page 241 and 242: XN62Lxxx STA TXRX STO SI AA 0x4a S
Page 243 and 244: XN62Lxxx 15.4.7.6 : 0x0b 0x01 AC
Page 245 and 246: XN62Lxxx 1. CONCLR 0x08 SI 2. 3.
Page 247 and 248: XN62Lxxx 16 RTC 16.1 1 Hz/1KHz RT
Page 249 and 250: XN62Lxxx 16.3.7 RTC Table 16-9: RT
Page 251 and 252: XN62Lxxx 17.2 Table 17-1: ADC
Page 253 and 254: XN62Lxxx 11:0 RESULT DONE 1 SELNO
Page 255 and 256: XN62Lxxx 31 DONE A/D 1 0 17.3.6 AD
Page 257 and 258: XN62Lxxx 9 DACCLR 0 1 0 0 10 DA
Page 259 and 260: XN62Lxxx Temperature Slope(°C LSB
Page 261 and 262: XN62Lxxx ACMP0_O 0 ACMP1_O 1
Page 263 and 264: XN62Lxxx 28 CMP0_RLT - 0 0 29 CMP
Page 265 and 266: XN62Lxxx - 2 0 • 16 1 (CT16B1)
Page 267 and 268: XN62Lxxx DMA 816 32 DMA 32 DMA
Page 269 and 270: XN62Lxxx 19.5.1 DMA DMA Table 19-
Page 271 and 272: XN62Lxxx [c] = 1 dma_sreq[c] DMA
Page 273 and 274: XN62Lxxx Table 19-14: (CHNL_PRIORI
Page 275: XN62Lxxx ... ... 27 19.7.4 DMA
Page 279 and 280: XN62Lxxx 00 = . 01 = . 10 = . 11 =
Page 281 and 282: XN62Lxxx Flash Control Address Addr
Page 283 and 284: XN62Lxxx 20.3.1 A/B Flash SRAM A,
Page 285 and 286: XN62Lxxx : #08H : #09H : #0AH : #0B
Page 287 and 288: XN62Lxxx : 0x15H : 20.4.7 : 0x16H
Page 289 and 290: XN62Lxxx : AB (32 ) (128 ) (128 ) -
Page 291 and 292: XN62Lxxx IAP iap_entry (command, r
Page 293: XN62Lxxx 22 1.0 Initial Release
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