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XN62Lxxx<br />
32 <br />
IC <br />
ARM + xDSP , 88K Flash,16K RAM<br />
<br />
1 <br />
1.1 <br />
XN62L ARM Cortex M0 32 <br />
ARM+xDSP <br />
100MHz xDSP 32 CORDIC<br />
<br />
24 <br />
PWM <br />
<br />
ARM XN62L <br />
XN62L <br />
12 ADC1210 DAC 2<br />
<br />
UART SPI/QSPI TWS <br />
WDT 4 /<br />
32 RTC 1%<br />
<br />
55 <br />
1.2 <br />
• ARM + xDSP<br />
• 100Mhz ARM Cortex-M0 <br />
• xDSP 32CRCSin<br />
CosArctan<br />
• 88KB Flash 16KB SRAM<br />
• DMA <br />
• Serial Wire Debug (SWD)<br />
• <br />
PWM<br />
• 3 PWM<br />
• 2 4PWM <br />
• <br />
• <br />
• PWMADC<br />
• <br />
• 21282<br />
<br />
• <br />
• <br />
• <br />
bootloader<br />
• F lashIn -System-Program (ISP) In-Application-Program (IAP)<br />
• <br />
ª 2010 Xinnova Technology Ltd. All rights reserved. The Xinnova logo is ed trademarks of Xinnova Technology Ltd. This Datasheet may be<br />
<br />
revised by subsequent versions or modifications without prior notice.
XN62Lxxx<br />
– <br />
0.5MHz 16MHz<br />
– 1% 20MHz <br />
– PLL 100MHz<br />
– 32K (RTC)<br />
• <br />
/<br />
– 2 16 / 2 32 /<br />
– / /<br />
– <br />
AB <br />
• <br />
– 3 12 1MHz ADC 12<br />
– 10 DAC1MHz<br />
– 2<br />
– -40°C ~ +120°C <br />
• <br />
– 4 <br />
UART – SP Iflash<br />
QSPI<br />
– TWS <br />
• /<br />
– 55 /<br />
• <br />
– <br />
– 12 <br />
– <br />
– BOD<br />
<br />
– POR<br />
– PMU<br />
• <br />
– (-40°C ~ +85°C)<br />
• <br />
• 3.3 V <br />
• 64 48<br />
LQFP <br />
2 www.xinnovatech.com
XN62Lxxx<br />
2 <br />
<br />
.<br />
Flash<br />
(bytes)<br />
SRAM<br />
(bytes)<br />
RTC<br />
UART<br />
SPI/<br />
QSPI<br />
TWS ADC PWM DAC<br />
<br />
DMA °C<br />
<br />
<br />
CRC<br />
<br />
32-<br />
CORDIC PMU PLL T/C GPIO<br />
<br />
XN62L912 88K 16K √ 4 2 1<br />
12ch<br />
ADC0,1,2<br />
22ch<br />
PWM0,1,2<br />
8fault<br />
√ 2 √ √ √ √ √ √ √ √ 4<br />
55<br />
GPIO0,1,2<br />
XN62L408 64K 12K √ 4 2 1<br />
8ch<br />
ADC0,1<br />
14ch<br />
PWM0,1<br />
8fault<br />
√ 2 √ √ √ √ √ √ √ √ 4<br />
39<br />
GPIO0,1<br />
www.xinnovatech.com 3
XN62Lxxx<br />
3 <br />
3.1 <br />
XN62L LQFP 64 LQFP 48 <br />
IO <br />
<br />
4 www.xinnovatech.com
XN62Lxxx<br />
www.xinnovatech.com 5<br />
3.2 LQFP 64 <br />
(XN62L912)<br />
LQFP64<br />
PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0/PWM_FAULT2<br />
16<br />
15<br />
14<br />
13<br />
12<br />
11<br />
10<br />
9<br />
8<br />
7<br />
5<br />
6<br />
4<br />
3<br />
1<br />
2<br />
PIO0_17/MOSI/RXD3<br />
PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/TXD3<br />
PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/RXD2<br />
VDD(IO)<br />
PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1/AD11<br />
PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1/AD10<br />
PIO2_9/CT32B1_CAP1/CT32B1_MAT1/PWM2_7/AD9<br />
PIO2_8/CT32B1_CAP0/CT32B1_MAT0/PWM2_6/AD8<br />
VDD(3V3)<br />
PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0<br />
VSS<br />
RTCXOUT<br />
PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1<br />
PIO1_4/AD6/PWM0_5/PWM1_5<br />
VSSIO<br />
PIO1_3/AD5<br />
PIO1_2/SWDIO/AD4<br />
R/PIO1_1/AD3/PWM0_4/PWM1_4<br />
RTCXIN<br />
49<br />
50<br />
51<br />
52<br />
53<br />
54<br />
55<br />
56<br />
57<br />
58<br />
60 59<br />
61<br />
62<br />
64 63<br />
R/PIO0_31/AD1/PWM1_7<br />
R/PIO0_30/AD0<br />
PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0<br />
PIO0_14/SCK/TXD2/CLKOUT<br />
RESET/PIO0_13/WAKEUP<br />
PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1/PWM1_6<br />
PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0<br />
PIO0_10/SCL<br />
R/PIO1_0/AD2<br />
PIO2_7/CT32B0_CAP3/CT32B0_MAT3/PWM2_5/RXD2<br />
PIO2_6/CT32B0_CAP2/CT32B0_MAT2/PWM2_4/TXD2<br />
PIO2_5/CT32B0_CAP1/CT32B0_MAT1/PWM1_5<br />
PIO2_4/CT32B0_CAP0/CT32B0_MAT0/PWM1_4<br />
33<br />
34<br />
35<br />
36<br />
37<br />
38<br />
39<br />
40<br />
41<br />
42<br />
44<br />
43<br />
45<br />
46<br />
48<br />
47<br />
PIO0_29/CT16B0_CAP1/CT16B0_MAT1/PWM1_6<br />
PIO0_0/PWM0_0/QSPI_CS<br />
PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0<br />
PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1<br />
PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_1/PWM1_4/QSPI_CLK<br />
PIO0_4/CT32B0_CAP3/CT32B0_MAT3/PWM0_2/PWM1_5/QSPI_WP<br />
PIO0_5/PWM0_3/QSPI_HOLD<br />
PIO0_6/CT32B1_CAP0/CT32B1_MAT0/PWM0_4/PWM1_2/QSPI_DI<br />
PIO0_7/CT32B1_CAP1/CT32B1_MAT1/PWM0_5/PWM1_3/QSPI_DO<br />
PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_6<br />
PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_7<br />
PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0<br />
PIO2_0/CT16B0_CAP0/CT16B0_MAT0/PWM1_0<br />
PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0/PWM_FAULT2/PWM1_1<br />
PIO2_2/CT16B1_CAP0/CT16B1_MAT0/TXD0/PWM_FAULT3/PWM1_2<br />
PIO2_3/CT16B1_CAP1/CT16B1_MAT1/PWM1_3<br />
32<br />
31<br />
30<br />
29<br />
28<br />
27<br />
26<br />
25<br />
24<br />
23<br />
21 22<br />
20<br />
19<br />
17 18<br />
XTALOUT<br />
VREF_ADC<br />
PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1<br />
PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2<br />
PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0<br />
PIO0_22/ACMP0_I3/PWM1_1<br />
PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1/PWM_FAULT3<br />
SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25<br />
SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26<br />
PIO0_27/ACMP0_O/DA0/PWM_FAULT0<br />
XTALIN<br />
PIO2_12/RXD1/PWM2_0<br />
PIO2_13/TXD1/PWM2_1<br />
PIO2_14/PWM2_2/TXD3<br />
PIO2_15/PWM2_3/RXD3
XN62Lxxx<br />
3.3 LQFP 48 (XN62L408)<br />
VSSIO<br />
VDD(IO)<br />
RTCXIN<br />
RTCXOUT<br />
VDD(3V3)<br />
VSS<br />
PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1<br />
PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0<br />
PIO1_4/AD6/PWM0_5/PWM1_5<br />
PIO1_3/AD5<br />
PIO1_2/SWDIO/AD4<br />
R/PIO1_1/AD3/PWM0_4/PWM1_4<br />
48 47 46 45 44 43 42 41 40 39 38 37<br />
XTALIN<br />
1<br />
36<br />
R/PIO1_0/AD2<br />
XTALOUT<br />
2<br />
35<br />
R/PIO0_31/AD1/PWM1_7<br />
VREF_CMP<br />
3<br />
34<br />
R/PIO0_30/AD0<br />
PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1<br />
4<br />
33<br />
PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0<br />
PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2<br />
5<br />
32<br />
PIO0_17/MOSI/RXD3<br />
PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0<br />
PIO0_22/ACMP0_I3/PWM1_1<br />
6<br />
7<br />
QFP48<br />
31<br />
30<br />
PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/TXD3<br />
PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/RXD2<br />
PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0/PWM_FAULT2<br />
8<br />
29<br />
PIO0_14/SCK/TXD2/CLKOUT<br />
PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1/PWM_FAULT3<br />
9<br />
28<br />
RESET/PIO0_13/WAKEUP<br />
SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25<br />
10<br />
27<br />
PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1/PWM1_6<br />
SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26<br />
11<br />
26<br />
PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0<br />
PIO0_27/ACMP0_O/DA0/PWM_FAULT0<br />
12<br />
13 14 15 16 17 18 19 20 21 22 23 24<br />
25<br />
PIO0_10/SCL<br />
PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0<br />
PIO0_29/CT16B0_CAP1/CT16B0_MAT1/PWM1_6<br />
PIO0_0/PWM0_0/QSPI_CS<br />
PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0<br />
PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1<br />
PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_1/PWM1_4/QSPI_CLK<br />
PIO0_4/CT32B0_CAP3/CT32B0_MAT3/PWM0_2/PWM1_5/QSPI_WP<br />
PIO0_5/PWM0_3/QSPI_HOLD<br />
PIO0_6/CT32B1_CAP0/CT32B1_MAT0/PWM0_4/PWM1_2/QSPI_DI<br />
PIO0_7/CT32B1_CAP1/CT32B1_MAT1/PWM0_5/PWM1_3/QSPI_DO<br />
PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_6<br />
PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_7<br />
6 www.xinnovatech.com
XN62Lxxx<br />
3.4 <br />
Table 3-1: <br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
PIO0_0/<br />
PWM0_0/<br />
QSPI_CS<br />
PIO0_1/<br />
RXD0/<br />
CT32B0_CAP0/<br />
CT32B0_MAT0<br />
PIO0_2/<br />
TXD0/<br />
CT32B0_CAP1/<br />
CT32B0_MAT1<br />
PIO0_3/<br />
CT32B0_CAP2/<br />
CT32B0_MAT2/<br />
PWM0_1/<br />
PWM1_4/<br />
QSPI_CLK<br />
PIO0_4/<br />
CT32B0_CAP3/<br />
CT32B0_MAT3/<br />
PWM0_2/<br />
PWM1_5/<br />
QSPI_WP<br />
PIO0_5/<br />
PWM0_3/<br />
QSPI_HOLD<br />
PIO0_6/<br />
CT32B1_CAP0/<br />
CT32B1_MAT0/<br />
PWM0_4/<br />
PWM1_2/<br />
QSPI_DI<br />
PIO0_7/<br />
CT32B1_CAP1/<br />
19 15 yes I/O I; PU PIO0_0 —/<br />
- O - PWM0_0 — PWM 0 , 0<br />
- O - QSPI_CS —QSPI <br />
20 16 yes I/O I; PU PIO0_1 —/<br />
- I - RXD0 —UART0 <br />
- I - CT32B0_CAP0 —32 0 <br />
0<br />
- O - CT32B0_MAT0 — 32 0 <br />
0<br />
21 17 yes I/O I; PU PIO0_2 — <br />
/<br />
- O - TXD0 —UART0 <br />
- I - CT32B0_CAP1 —32 0 <br />
1<br />
- O - CT32B0_MAT1 —32 0 <br />
1<br />
22 18 yes I/O I; PU PIO0_3 — <br />
/ .<br />
- I - CT32B0_CAP2 —32 0 <br />
2<br />
- O - CT32B0_MAT2 —32 0 <br />
2<br />
- O - PWM0_1 — PWM 0 , 1<br />
- O - PWM1_4 — PWM 1 , 4<br />
- O - QSPI_CLK —QSPI <br />
23 19 yes I/O I; PU PIO0_4 — <br />
/<br />
- I - CT32B0_CAP3 —32 0 <br />
3<br />
- O - CT32B0_MAT3 —32 0 <br />
3<br />
- O - PWM0_2 — PWM 0 , 2<br />
- O - PWM1_5 — PWM 1 , 5<br />
- I/O - QSPI_WP —QSPI IO2<br />
24 20 yes I/O I; PU PIO0_5 — <br />
/<br />
- O - PWM0_3 — PWM 0 , 3<br />
- I/O - QSPI_HOLD —QSPI IO3<br />
25 21 yes I/O I; PU PIO0_6 — <br />
/<br />
- I - CT32B1_CAP0 —32 1 <br />
0<br />
- O - CT32B1_MAT0 —32 1 <br />
0<br />
- O - PWM0_4 — PWM 0 , 4<br />
- O - PWM1_2 — PWM 1 , 2<br />
- I/O - QSPIDI —QSPI <br />
IO0<br />
26 22 yes I/O I; PU PIO0_7 — <br />
/<br />
- I - CT32B1_CAP1 —32 1 <br />
1<br />
www.xinnovatech.com 7
XN62Lxxx<br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
CT32B1_MAT1/<br />
PWM0_5/<br />
PWM1_3/<br />
QSPI_DO<br />
PIO0_8/<br />
RXD1/<br />
CT32B1_CAP2/<br />
CT32B1_MAT2/<br />
PWM0_6<br />
PIO0_9/<br />
TXD1/<br />
CT32B1_CAP3/<br />
CT32B1_MAT3/<br />
PWM0_7<br />
PIO0_10/<br />
SCL<br />
PIO0_11/<br />
SDA/<br />
CT16B0_CAP0/<br />
CT16B0_MAT0<br />
PIO0_12/<br />
CLKOUT/<br />
CT16B0_CAP1/<br />
CT16B0_MAT1<br />
PWM1_6<br />
RESET/<br />
PIO0_13/<br />
WAKEUP<br />
PIO0_14/<br />
SCK/<br />
CLKOUT/<br />
TXD2<br />
PIO0_15/<br />
SSEL/<br />
CT16B1_CAP0/<br />
CT16B1_MAT0/<br />
RXD2<br />
- O - CT32B1_MAT1 —32 1 <br />
1<br />
- O - PWM0_5 — PWM 0 , 5<br />
- O - PWM1_3 — PWM 1 , 3<br />
- I/O - QSPI_DO —QSPI IO1<br />
27 23 yes I/O I; PU PIO0_8 — <br />
/<br />
- I - RXD1 —UART1 <br />
- I - CT32B1_CAP2 —32 1 <br />
2<br />
- O - CT32B1_MAT2 —32 1 <br />
2<br />
- O - PWM0_6 — PWM 0 , 6<br />
28 24 yes I/O I; PU PIO0_9 — <br />
/<br />
- O - TXD1 —UART1 <br />
- I - CT32B1_CAP3 —32 1 <br />
3<br />
- O - CT32B1_MAT3 —32 1 <br />
3<br />
- O - PWM0_7 — PWM 0 , 7<br />
37 25 yes I/O I; IA PIO0_10 — <br />
/<br />
- I/O - SCL —TWS /<br />
38 26 yes I/O I; IA PIO0_11 — <br />
/<br />
- I/O - SDA —TWS <br />
/<br />
- I - CT16B0_CAP0 —16 0 <br />
0<br />
- O - CT16B0_MAT0 —16 0 <br />
0<br />
39 27 - I/O I; PU PIO0_12 — <br />
/<br />
- O - CLKOUT —<br />
- I - CT16B0_CAP1 —16 0 <br />
1<br />
- O - CT16B0_MAT1 —16 0 <br />
1<br />
- O - PWM1_6 — PWM 1 , 6<br />
40 28 - I I; PU RESET —<br />
- I/O - PIO0_13 — <br />
/<br />
- I - WAKEUP —<br />
41 29 - I/O I; PU PIO0_14 — <br />
/<br />
- I/O - SCK —SPI <br />
- O - CLKOUT —<br />
- O - TXD2 —UART2 <br />
42 30 - I/O I; PU PIO0_15 — <br />
/<br />
- I/O - SSEL — SPI <br />
- I - CT16B1_CAP0 —16 1 <br />
0<br />
- O - CT16B1_MAT0 —16 1 <br />
0<br />
- I - RXD2 —UART2 <br />
PIO0_16/ 43 31 - I/O I; PU PIO0_16 — <br />
/<br />
8 www.xinnovatech.com
XN62Lxxx<br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
MISO/<br />
CT16B1_CAP1/<br />
CT16B1_MAT1/<br />
TXD3<br />
PIO0_17/<br />
MOSI/<br />
RXD3<br />
PIO0_18/<br />
SWCLK/<br />
CT32B0_CAP0/<br />
CT32B0_MAT0<br />
PIO0_19/<br />
ACMP0_I0/<br />
CT32B0_CAP1/<br />
CT32B0_MAT1<br />
PIO0_20/<br />
ACMP0_I1/<br />
CT32B0_CAP2/<br />
CT32B0_MAT2<br />
PIO0_21/<br />
ACMP0_I2/<br />
CT32B0_CAP3/<br />
CT32B0_MAT3<br />
PIO0_22/<br />
ACMP0_I3<br />
PIO0_23/<br />
ACMP1_I0/<br />
CT32B1_CAP0/<br />
CT32B1_MAT0<br />
PIO0_24/<br />
ACMP1_I1/<br />
CT32B1_CAP1/<br />
CT32B1_MAT1<br />
SWDIO/<br />
ACMP1_I2/<br />
CT32B1_CAP2/<br />
CT32B1_MAT2/<br />
PIO0_25<br />
- I/O - MISO — SPI <br />
- I - CT16B1_CAP1 —16 1 <br />
1<br />
- O - CT16B1_MAT1 —16 1 <br />
1<br />
- O - TXD3 —UART3 <br />
44 32 - I/O I; PU PIO0_17 — <br />
/<br />
- I/O - MOSI —SPI <br />
- I - RXD3 —UART3 <br />
45 33 - I/O I; PU PIO0_18 — <br />
/<br />
- I - SWCLK — SWD <br />
- I - CT32B0_CAP0 —32 0 <br />
0<br />
- O - CT32B0_MAT0 —32 0 <br />
0<br />
4 4 - I/O I; PU PIO0_19 — <br />
/<br />
- I - ACMP0_I0 — 0 0<br />
- I - CT32B0_CAP1 —32 0 <br />
1<br />
- O - CT32B0_MAT1 —32 0 <br />
1<br />
5 5 - I/O I; PU PIO0_20 — <br />
/<br />
- I - ACMP0_I1 — 0 1<br />
- I - CT32B0_CAP2 —32 0 <br />
2<br />
- O - CT32B0_MAT2 —32 0 <br />
2<br />
6 6 - I/O I; PU PIO0_21 — <br />
/<br />
- I - ACMP0_I2 — 0 2<br />
- I - CT32B0_CAP3 —32 0 <br />
3<br />
- O - CT32B0_MAT3 —32 0 <br />
3<br />
7 7 - I/O I; PU PIO0_22 — <br />
/<br />
- I - ACMP0_I3 — 0 3<br />
8 8 - I/O I; PU PIO0_23 — <br />
/<br />
- I - ACMP1_I0 — 1 0<br />
- I - CT32B1_CAP0 —32 1 <br />
0<br />
- O - CT32B1_MAT0 —32 1 <br />
0<br />
9 9 - I/O I; PU PIO0_24 — <br />
/<br />
- I - ACMP1_I1 — 1 1<br />
- I - CT32B1_CAP1 —32 1 <br />
1<br />
- O - CT32B1_MAT1 —32 1 <br />
1<br />
10 10 - I/O I; PU SWDIO —SWD <br />
- I - ACMP1_I2 — 1 2<br />
- I - CT32B1_CAP2 —32 1 <br />
2<br />
- O - CT32B1_MAT2 —32 1 <br />
2<br />
- I/O - PIO0_25 — <br />
/<br />
www.xinnovatech.com 9
XN62Lxxx<br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
SWCLK/<br />
ACMP1_I3/<br />
CT32B1_CAP3/<br />
CT32B1_MAT3/<br />
PIO0_26<br />
PIO0_27/<br />
ACMP0_O/<br />
DA0<br />
PIO0_28/<br />
ACMP1_O/<br />
CT16B0_CAP0/<br />
CT16B0_MAT0<br />
PIO0_29/<br />
CT16B0_CAP1/<br />
CT16B0_MAT1<br />
R/<br />
PIO0_30/<br />
AD0<br />
R/<br />
PIO0_31/<br />
AD1/<br />
PWM1_7<br />
R/<br />
PIO1_0/<br />
AD2<br />
R/<br />
PIO1_1/<br />
AD3/<br />
PWM0_4/<br />
PWM1_4<br />
PIO1_2/<br />
SWDIO/<br />
AD4<br />
PIO1_3/<br />
AD5/<br />
PIO1_4/<br />
AD6/<br />
PWM0_5/<br />
11 11 - I I; PU SWCLK —SWD <br />
- I - ACMP1_I3 — 1 3<br />
- I - CT32B1_CAP3 —32 1 <br />
3<br />
- O - CT32B1_MAT3 —32 1 <br />
3<br />
- I/O PIO0_26 — <br />
/<br />
12 12 - I/O I; PU PIO0_27 — <br />
/<br />
- O - ACMP0_O — 0 <br />
- O - DA0 — DA <br />
17 13 - I/O I; PU PIO0_28 — <br />
/ . <br />
- O - ACMP1_O — 1 <br />
- I - CT16B0_CAP0 —16 0 <br />
0<br />
- O - CT16B0_MAT0 —16 0 <br />
0<br />
18 14 - I/O I; PU PIO0_29 — <br />
/ . <br />
- I - CT16B0_CAP1 —16 0 <br />
1<br />
- O - CT16B0_MAT1 —16 0 <br />
1<br />
46 34 - I I; PU R —<br />
- I/O - PIO0_30 — <br />
/<br />
- I - AD0 —A/D <br />
0<br />
47 35 - I I; PU R —<br />
- I/O - PIO0_31 — <br />
/<br />
- I - AD1 —A/D <br />
1<br />
- O - PWM1_7 — PWM 1 , 7<br />
48 36 - I I; PU R —<br />
- I/O - PIO1_0 — <br />
/<br />
- I - AD2 —A/D <br />
2<br />
49 37 - I I; PU R —<br />
- I/O - PIO1_1 — <br />
/<br />
- I - AD3 —A/D <br />
3<br />
- O - PWM0_4 — PWM 0 , 4<br />
- O - PWM1_4 — PWM 1 , 4<br />
50 38 - I/O I; PU PIO1_2 — <br />
/<br />
- I/O - SWDIO —SWD <br />
- I - AD4 —A/D <br />
4<br />
51 39 - I/O I; PU PIO1_3 — <br />
/<br />
- I - AD5 —A/D <br />
5<br />
52 40 - I/O I; PU PIO1_4 — <br />
/<br />
- I - AD6 —A/D <br />
6<br />
- O - PWM0_5 — PWM 0 , 5<br />
10 www.xinnovatech.com
XN62Lxxx<br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
PWM1_5 - O - PWM1_5 — PWM 1 , 5<br />
PIO1_5/<br />
AD7/<br />
CT16B1_CAP0/<br />
CT16B1_MAT0/<br />
PWM_FAULT1<br />
PIO1_6/<br />
CT16B1_CAP1/<br />
CT16B1_MAT1<br />
PIO2_0/<br />
CT16B0_CAP0/<br />
CT16B0_MAT0/<br />
PWM1_0<br />
PIO2_1/<br />
CT16B0_CAP1/<br />
CT16B0_MAT1/<br />
RXD0/<br />
PWM_FAULT2/<br />
PWM1_1<br />
PIO2_2/<br />
CT16B1_CAP0/<br />
CT16B1_MAT0/<br />
TXD0/<br />
PWM_FAULT3/<br />
PWM1_2<br />
PIO2_3/<br />
CT16B1_CAP1/<br />
CT16B1_MAT1/<br />
PWM1_3<br />
PIO2_4/<br />
CT32B0_CAP0/<br />
CT32B0_MAT0/<br />
PWM1_4<br />
PIO2_5/<br />
CT32B0_CAP1/<br />
CT32B0_MAT1/<br />
PWM1_5<br />
53 41 - I/O I; PU PIO1_5 — <br />
/<br />
- I - AD7 —A/D <br />
7<br />
- I - CT16B1_CAP0 —16 1 <br />
0<br />
- O - CT16B1_MAT0 —16 1 <br />
0<br />
- I - PWM_FAULT1 — PWM 1<br />
54 42 - I/O I; PU PIO1_6 — <br />
/<br />
- I - CT16B1_CAP1 —16 1 <br />
1<br />
- O - CT16B1_MAT1 —16 1 <br />
1<br />
29 - - I/O I; PU PIO2_0 — <br />
/<br />
- I - CT16B0_CAP0 —16 0 <br />
0<br />
- O - CT16B0_MAT0 —16 0 <br />
0<br />
- O - PWM1_0 — PWM 1 , 0<br />
30 - - I/O I; PU PIO2_1 — <br />
/<br />
- I - CT16B0_CAP1 —16 0 <br />
1<br />
- O - CT16B0_MAT1 —16 0 <br />
1<br />
- I - RXD0 —UART0 <br />
- I - PWM_FAULT2 — PWM 2<br />
- O - PWM1_1 — PWM 1 , 1<br />
31 - - I/O I; PU PIO2_2 — <br />
/<br />
- I - CT16B1_CAP0 —16 1 <br />
0<br />
- O - CT16B1_MAT0 —16 1 <br />
0<br />
- O - TXD0 —UART0 <br />
- I - PWM_FAULT3 — PWM 3<br />
- O - PWM1_2 — PWM 1 , 2<br />
32 - - I/O I; PU PIO2_3 — <br />
/<br />
- I - CT16B1_CAP1 —16 1 <br />
1<br />
- O - CT16B1_MAT1 —16 1 <br />
1<br />
- O - PWM1_3 — PWM 1 , 3<br />
33 - - I/O I; PU PIO2_4 — <br />
/<br />
- I - CT32B0_CAP0 —32 0 <br />
0<br />
- O - CT32B0_MAT0 —32 0 <br />
0<br />
- O - PWM1_4 — PWM 1 , 4<br />
34 - - I/O I; PU PIO2_5 — <br />
/<br />
- I - CT32B0_CAP1 —32 0 <br />
1<br />
- O - CT32B0_MAT1 —32 0 <br />
1<br />
- O - PWM1_5 — PWM 1 , 5<br />
PIO2_6/ 35 - - I/O I; PU PIO2_6 — <br />
/<br />
www.xinnovatech.com 11
XN62Lxxx<br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
CT32B0_CAP2/<br />
CT32B0_MAT2/<br />
TXD2/<br />
PWM2_4<br />
PIO2_7/<br />
CT32B0_CAP3/<br />
CT32B0_MAT3/<br />
RXD2/<br />
PWM2_5<br />
PIO2_8/<br />
CT32B1_CAP0/<br />
CT32B1_MAT0/<br />
PWM2_6/<br />
AD8<br />
PIO2_9/<br />
CT32B1_CAP1/<br />
CT32B1_MAT1/<br />
PWM2_7/<br />
AD9<br />
PIO2_10/<br />
CT32B1_CAP2/<br />
CT32B1_MAT2/<br />
TXD1/<br />
AD10<br />
PIO2_11/<br />
CT32B1_CAP3/<br />
CT32B1_MAT3/<br />
RXD1/<br />
AD11<br />
PIO2_12/<br />
RXD1/<br />
PWM2_0<br />
PIO2_13/<br />
TXD1/<br />
PWM2_1<br />
PIO2_14/<br />
TXD3/<br />
PWM2_2<br />
- I - CT32B0_CAP2 —32 0 <br />
2<br />
- O - CT32B0_MAT2 —32 0 <br />
2<br />
- O - TXD2 —UART2 <br />
- O - PWM2_4 — PWM 2 , 4<br />
36 - - I/O I; PU PIO2_7 — <br />
/<br />
- I - CT32B0_CAP3 —32 0 <br />
3<br />
- O - CT32B0_MAT3 —32 0 <br />
3<br />
- I - RXD2 —UART2 <br />
- O - PWM2_5 — PWM 2 , 5<br />
59 - - I/O I; PU PIO2_8 — <br />
/<br />
- I - CT32B1_CAP0 —32 1 <br />
0<br />
- O - CT32B1_MAT0 —32 1 <br />
0<br />
- O - PWM2_6 — PWM 2 , 6<br />
- I - AD8 —A/D <br />
8<br />
60 - - I/O I; PU PIO2_9 — <br />
/<br />
- I - CT32B1_CAP1 —32 1 <br />
1<br />
- O - CT32B1_MAT1 —32 1 <br />
1<br />
- O - PWM2_7 — PWM 2 , 7<br />
- I - AD9 —A/D <br />
9<br />
61 - - I/O I; PU PIO2_10 — <br />
/<br />
- I - CT32B1_CAP2 —32 1 <br />
2<br />
- O - CT32B1_MAT2 —32 1 <br />
2<br />
- O - TXD1 —UART1 <br />
- I - AD10 —A/D <br />
10<br />
62 - - I/O I; PU PIO2_11 — <br />
/<br />
- I - CT32B1_CAP3 —32 1 <br />
3<br />
- O - CT32B1_MAT3 —32 1 <br />
3<br />
- I - RXD1 —UART1 <br />
- I - AD11 —A/D <br />
11<br />
13 - - I/O I; PU PIO2_12 — <br />
/<br />
- I - RXD1 —UART1 <br />
- O - PWM2_0 — PWM 2 , 0<br />
14 - - I/O I; PU PIO2_13 — <br />
/<br />
- O - TXD1 —UART1 <br />
- O - PWM2_1 — PWM 2 , 1<br />
15 - - I/O I; PU PIO2_14 — <br />
/<br />
- O - TXD3 —UART3 <br />
- O - PWM2_2 — PWM 2 , 2<br />
12 www.xinnovatech.com
XN62Lxxx<br />
<br />
QFP64<br />
QFP48<br />
<br />
<br />
<br />
<br />
<br />
PIO2_15/<br />
RXD3/<br />
PWM2_3<br />
16 - - I/O I; PU PIO2_15 — <br />
/<br />
- I - RXD3 —UART3 <br />
- O - PWM2_3 — PWM 2 , 3<br />
RTCXIN 58 46 - O - 32 KHz <br />
RTCXOUT 57 45 - I - 32 KHz <br />
XTALIN 1 1 - I - <br />
XTALOUT 2 2 - O - <br />
V REF_ADC 3 3 - I - ADC <br />
V DD(IO) 63 47 - I - IO <br />
V DD(3V3) 56 44 - I - 3.3V <br />
V SSIO 64 48 - I - <br />
V SS 55 43 - I - <br />
3.5 <br />
MCU <br />
IOCONFIG <br />
SWD RESET <br />
<br />
GPIO<br />
Table 3-2: <br />
<br />
PWM PWM0_0 O PIO0_0<br />
PWM0_1 O PIO0_3<br />
PWM0_2 O PIO0_4<br />
PWM0_3 O PIO0_5<br />
PWM0_4 O PIO0_6<br />
PWM0_5 O PIO0_7<br />
PWM0_6 O PIO0_8<br />
PWM0_7 O PIO0_9<br />
PWM1_0 O PIO0_21 PIO2_0<br />
PWM1_1 O PIO0_22 PIO2_1<br />
PWM1_2 O PIO0_6 PIO2_2<br />
PWM1_3 O PIO0_7 PIO2_3<br />
PWM1_4 O PIO0_3 PIO2_4<br />
PWM1_5 O PIO0_4 PIO2_5<br />
PWM1_6 O PIO0_29 PIO0_12<br />
PWM1_7 O PIO0_31<br />
PWM2_0 O PIO2_12<br />
PWM2_1 O PIO2_13<br />
www.xinnovatech.com 13
XN62Lxxx<br />
PWM2_2 O PIO2_14<br />
PWM2_3 O PIO2_15<br />
PWM2_4 O PIO2_6<br />
PWM2_5 O PIO2_7<br />
PWM2_6 O PIO2_8<br />
PWM2_7 O PIO2_9<br />
PWM_FAULT0 I PIO0_27<br />
PWM_FAULT1 I PIO1_6<br />
PWM_FAULT2 I PIO0_23 PIO2_1<br />
PWM_FAULT3 I PIO0_24 PIO2_2<br />
ACMP0_I0 I PIO0_19<br />
ACMP0_I1 I PIO0_20<br />
ACMP0_I2 I PIO0_21<br />
ACMP0_I3 I PIO0_22<br />
ACMP0_O O PIO0_27<br />
ACMP1_I0 I PIO0_23<br />
ACMP1_I1 I PIO0_24<br />
ACMP1_I2 I PIO0_25<br />
ACMP1_I3 I PIO0_26<br />
ACMP1_O O PIO0_28<br />
ADC AD0 I PIO0_30<br />
AD1 I PIO0_31<br />
AD2 I PIO1_0<br />
AD3 I PIO1_1<br />
AD4 I PIO1_2<br />
AD5 I PIO1_3<br />
AD6 I PIO1_4<br />
AD7 I PIO1_5<br />
AD8 I PIO2_8<br />
AD9 I PIO2_9<br />
AD10 I PIO2_10<br />
AD11 I PIO2_11<br />
DAC DA0 O PIO0_27<br />
CT16B0 CT16B0_CAP0 I PIO0_11 PIO0_28 PIO2_0<br />
CT16B0_CAP1 I PIO0_12 PIO0_29 PIO2_1<br />
CT16B0_MAT0 O PIO0_11 PIO0_28 PIO2_0<br />
CT16B0_MAT1 O PIO0_12 PIO0_29 PIO2_1<br />
CT16B1 CT16B1_CAP0 I PIO0_15 PIO1_5 PIO2_2<br />
CT16B1_CAP1 I PIO0_16 PIO1_6 PIO2_3<br />
CT16B1_MAT0 O PIO0_15 PIO1_5 PIO2_2<br />
14 www.xinnovatech.com
XN62Lxxx<br />
CT16B1_MAT1 O PIO0_16 PIO1_6 PIO2_3<br />
CT32B0 CT32B0_CAP0 I PIO0_1 PIO0_18 PIO2_4<br />
CT32B0_CAP1 I PIO0_2 PIO0_19 PIO2_5<br />
CT32B0_CAP2 I PIO0_3 PIO0_20 PIO2_6<br />
CT32B0_CAP3 I PIO0_4 PIO0_21 PIO2_7<br />
CT32B0_MAT0 O PIO0_1 PIO0_18 PIO2_4<br />
CT32B0_MAT1 O PIO0_2 PIO0_19 PIO2_5<br />
CT32B0_MAT2 O PIO0_3 PIO0_20 PIO2_6<br />
CT32B0_MAT3 O PIO0_4 PIO0_21 PIO2_7<br />
CT32B1 CT32B1_CAP0 I PIO0_6 PIO0_23 PIO2_8<br />
CT32B1_CAP1 I PIO0_7 PIO0_24 PIO2_9<br />
CT32B1_CAP2 I PIO0_8 PIO0_25 PIO2_10<br />
CT32B1_CAP3 I PIO0_9 PIO0_26 PIO2_11<br />
CT32B1_MAT0 O PIO0_6 PIO0_23 PIO2_8<br />
CT32B1_MAT1 O PIO0_7 PIO0_24 PIO2_9<br />
CT32B1_MAT2 O PIO0_8 PIO0_25 PIO2_10<br />
CT32B1_MAT3 O PIO0_9 PIO0_26 PIO2_11<br />
UART0 RXD0 I PIO0_1 PIO2_1<br />
TXD0 O PIO0_2 PIO2_2<br />
UART1 RXD1 I PIO0_8 PIO2_11 PIO2_12<br />
TXD1 O PIO0_9 PIO2_10 PIO2_13<br />
UART2 RXD2 I PIO0_15 PIO2_7<br />
TXD2 O PIO0_14 PIO2_6<br />
UART3 RXD3 I PIO0_17 PIO2_15<br />
TXD3 O PIO0_16 PIO2_14<br />
SPI SCK I/O PIO0_14<br />
MISO I/O PIO0_16<br />
MOSI I/O PIO0_17<br />
SSEL I/O PIO0_15<br />
TWS SCL I/O PIO0_10<br />
SDA I/O PIO0_11<br />
SWD SWCLK I PIO0_26 PIO0_18<br />
SWDIO I/O PIO0_25 PIO1_2<br />
QSPI QSPI_CLK O PIO0_3<br />
QSPI_CS O PIO0_0<br />
QSPI_DI(IO 0) I/O PIO0_6<br />
QSPI_DO(IO 1) I/O PIO0_7<br />
QSPI_WP(IO 2) I/O PIO0_4<br />
QSPI_HOLD(IO 3) I/O PIO0_5<br />
www.xinnovatech.com 15
XN62Lxxx<br />
4 <br />
SWD<br />
XTALIN<br />
XTALOUT RESET<br />
TEST/DEBUG<br />
INTERFACE<br />
IRC, OSILLATORS<br />
BOD<br />
POR<br />
CLOCK<br />
GENERATION,<br />
POWER CONTROL<br />
SYSTEM<br />
FUNCTION<br />
CLKOUT<br />
ARM<br />
Cortex-M0<br />
DMA<br />
CONTROLLER<br />
88K/64K<br />
APP. FLASH<br />
8K<br />
BOOT<br />
16K/12K<br />
SRAM<br />
AHB-LITE BUS<br />
xDSP<br />
(CRC/Sin/Cos/Arctan/<br />
Filter/32-bit Divider)<br />
AHB-APB<br />
BRIDGE<br />
Temperature<br />
Sensor<br />
HIGH speed<br />
GPIO<br />
GPIO_port<br />
SPI<br />
12-bit ADC0<br />
QSPI<br />
12-bit ADC1<br />
12-bit ADC2 (1)<br />
AD[11:0]<br />
UART0<br />
PWM0<br />
PWM0[7:0]<br />
UART1<br />
PWM1<br />
PWM1[7:0]<br />
UART2<br />
PWM2 (1)<br />
PWM2[7:0]<br />
UART3<br />
TWS<br />
10-bit DAC<br />
DA<br />
RTCLKIN<br />
RTCLKOUT<br />
WATCHDOG<br />
32KHz<br />
OSCILLATOR<br />
RTC<br />
COMPARATOR0/1<br />
ACMP0_I[3:0]<br />
ACMP1_I[3:0]<br />
ACMP0_O<br />
ACMP1_O<br />
SYSTEM CONTROL<br />
32-bit<br />
COUNTER/TIMER<br />
4xMAT<br />
4xCAP<br />
32-bit<br />
COUNTER/TIMER<br />
4xMAT<br />
4xCAP<br />
16-bit<br />
COUNTER/TIMER<br />
2xMAT<br />
2xCAP<br />
16-bit<br />
COUNTER/TIMER<br />
2xMAT<br />
2xCAP<br />
(1): XN62L912 only.<br />
FFigu<br />
re 4-1: XN62L <br />
16 www.xinnovatech.com
XN62Lxxx<br />
5 <br />
5.1 ARM Cortex-M0 <br />
Cortex M0 32 <br />
RISC <br />
AMBA-Lite <br />
<br />
Thumb Cortex-M Thread<br />
Handler <br />
Handler Handler <br />
Thread Thread<br />
<br />
M0 <br />
Power<br />
Management<br />
Interface<br />
Connection to<br />
Debugger<br />
Wakeup Interrupt<br />
Controller<br />
SWD Debug<br />
Interface<br />
Interrupt<br />
Request and<br />
NMI<br />
Nested Vector<br />
Interrupt Controller<br />
(NVIC)<br />
Cortex-M0<br />
Processor Core<br />
Debug Subsystem<br />
Internal Bus System<br />
AHB LITE Bus<br />
Interface<br />
Cortex-M0<br />
Memory and<br />
Peripherals<br />
ARM Cortex-M0 :<br />
• ARMv6-M Thumb<br />
• Thumb-2 <br />
• ARMv6-M 24- SysTick<br />
• 32-<br />
Figure 5-1: Cortex M0 <br />
www.xinnovatech.com 17
XN62Lxxx<br />
• little<br />
-endian<br />
• <br />
• <br />
• CC<br />
-ABIARMv6 -MC<br />
• <br />
WFI<br />
WFE<br />
• NVIC:<br />
– 32 <br />
4<br />
– NMI<br />
– <br />
– (WIC),<br />
<br />
• <br />
– <br />
– <br />
– PCSR<br />
– <br />
• :<br />
– 32AMBA-<br />
3 ABH-Lite.<br />
– DAP(Debug Access Port) 32.<br />
5.2 <br />
XN62L <br />
4GB F<br />
lash SRAM APB<br />
AHB<br />
<br />
M0 AHB 2M <br />
128 GPIO<br />
xDSP DMA AHB APB<br />
512K <br />
APB 16K <br />
word<br />
<br />
8KB ISP<br />
IAP XN62L Flash 88KBSRAM<br />
16KBFlashSRAM <br />
32 <br />
XN62L <br />
18 www.xinnovatech.com
XN62Lxxx<br />
Private peripheral<br />
Reserved<br />
0xE010 0000<br />
4GB<br />
Reserved<br />
Private peripheral<br />
Reserved<br />
AHB peripheral<br />
Reserved<br />
APB peripheral<br />
Reserved<br />
8KB Boot rom<br />
Reserved<br />
Reserved<br />
16KB SRAM<br />
Reserved<br />
88KB On-chip<br />
0xFFFF FFFF<br />
0xE010 0000<br />
0xE000 0000<br />
0x5008 0000<br />
0x5000 0000<br />
0x4008 0000<br />
0x4000 0000<br />
0x1FFF 2000<br />
0x1FFF 0000<br />
0x1FFE 0000<br />
0x1000 4000<br />
0x1000 0000<br />
0x0001 6000<br />
0x0000 0000<br />
Interrupt vectors<br />
0x0000 00C0<br />
0x0000 0000<br />
SCB<br />
NVIC<br />
System Tick<br />
Reserved<br />
AHB peripheral<br />
xDSP<br />
Flash<br />
Reserved<br />
GPIO PIO2<br />
GPIO PIO1<br />
GPIO PIO0<br />
APB peripheral<br />
Reserved<br />
QSPI<br />
UART3<br />
UART2<br />
DAC0<br />
ADC2<br />
ADC1<br />
PWM2<br />
PWM1<br />
PWM0<br />
Comparator 0/1<br />
RTC<br />
DMA<br />
System control<br />
IO config<br />
SPI<br />
Reserved<br />
PMU<br />
Reserved<br />
0xE000 EE00<br />
0xE000 ED00<br />
0xE000 E100<br />
0xE000 E000<br />
0xE000 0000<br />
0x5008 0000<br />
0x5007 0000<br />
0x5006 0000<br />
0x5003 0000<br />
0x5002 0000<br />
0x5001 0000<br />
0x5000 0000<br />
0x4008 0000<br />
0x4007 C000<br />
0x4007 8000<br />
0x4007 4000<br />
0x4007 0000<br />
0x4006 C180<br />
0x4006 8000<br />
0x4006 4000<br />
0x4006 0000<br />
0x4005 C000<br />
0x4005 8000<br />
0x4005 4000<br />
0x4005 0000<br />
0x4004 C000<br />
0x4004 8000<br />
0x4004 4000<br />
0x4004 0000<br />
0x4003 C000<br />
0x4003 8000<br />
ADC0<br />
32-bit timer/counter<br />
32-bit timer/counter<br />
16-bit timer/counter<br />
16-bit timer/counter<br />
UART1<br />
UART0<br />
WDT<br />
TWS<br />
0x4002 4000<br />
0x4002 0000<br />
0x4001 C000<br />
0x4001 8000<br />
0x4001 4000<br />
0x4001 0000<br />
0x4000 C000<br />
0x4000 8000<br />
0x4000 4000<br />
0x4000 0000<br />
Figure 5-2: <br />
www.xinnovatech.com 19
XN62Lxxx<br />
Table 5-1: <br />
<br />
0x00000000 ~ 0x00015FFF Flash <br />
0x10000000 ~ 0x10003FFF<br />
SRAM <br />
0x10004000 ~ 0x1FFEFFFF <br />
0x1FFF0000 ~ 0x1FFF1FFF<br />
0x40000000 ~ 0x40003FFF<br />
Boot<br />
loader<br />
TWS<br />
0x40004000 ~ 0x40007FFF <br />
0x40008000 ~ 0x4000BFFF<br />
0x4000C000 ~ 0x4000FFFF<br />
0x40010000 ~ 0x40013FFF<br />
0x40014000 ~ 0x40017FFF<br />
0x40018000 ~ 0x4001BFFF<br />
0x4001C000 ~ 0x4001FFFF<br />
0x40020000 ~ 0x40023FFF<br />
UART 0<br />
UART 1<br />
16- 0<br />
16- 1<br />
32- 0<br />
32- 1<br />
ADC0<br />
0x40024000 ~ 0x40037FFF <br />
0x40038000 ~ 0x4003BFFF<br />
PMU<br />
0x4003C000 ~ 0x4003FFFF <br />
0x40040000 ~ 0x40043FFF<br />
0x40044000 ~ 0x40047FFF<br />
SPI<br />
IOCONFIG<br />
0x40048000 ~ 0x4004BFFF <br />
0x4004C000 ~ 0x4004FFFF DMA <br />
0x40050000 ~ 0x40053FFF<br />
0x40054000 ~ 0x40057FFF<br />
Real Timer Clock<br />
0,1<br />
0x40058000 ~ 0x4005BFFF PWM 0<br />
0x4005C000 ~ 0x4005FFFF PWM 1<br />
0x40060000 ~ 0x40063FFFF<br />
0x40064000 ~ 0x40067FFFF<br />
0x40068000 ~ 0x4006BFFFF<br />
0x4006C000 ~ 0x4006FFFFF<br />
0x40070000 ~ 0x40073FFFF<br />
0x40074000 ~ 0x40077FFFF<br />
0x40078000 ~ 0x40078BFFF<br />
PWM2<br />
ADC1<br />
ADC2<br />
DAC<br />
UART 2<br />
UART 3<br />
QSPI<br />
0x4007C000 ~ 0x4FFFFFFF <br />
0x50000000 ~ 0x5000FFFF GPIO 0<br />
0x50010000 ~ 0x5001FFFF GPIO 1<br />
0x50020000 ~ 0x5002FFFF GPIO 2<br />
0x50030000 ~ 0x5006FFFF <br />
0x50070000 ~ 0x5007FFFF<br />
xDSP<br />
0x50080000 ~ 0xFFFFFFFF <br />
20 www.xinnovatech.com
XN62Lxxx<br />
0xE000E000 ~ 0xE000E0FF<br />
0xE000E100 ~ 0xE000E4FF<br />
0xE000ED00 ~ 0xE000EE00<br />
System Tick Timer<br />
NVIC<br />
M0 SCB <br />
www.xinnovatech.com 21
XN62Lxxx<br />
5.3 Cortex-M0 <br />
5.3.1 <br />
Cortex-M0 <br />
(SCB) M0 <br />
SCB <br />
Table 5-2: Cortex M0 SCB ( 0xE000-ED00)<br />
<br />
CPUID RO 0x00 M0 0x410CC200<br />
ICSR RW 0x04 NMI 0x00000000<br />
AIRCR RW 0x0C 0xFA050000<br />
SCR RW 0x10 0x00000000<br />
CCR RO 0x14 0x00000204<br />
SHPR2 RW 0x1C 2 0x00000000<br />
SHPR3 RW 0x20 <br />
3 0x00000000<br />
5.3.2 CPUID <br />
CPUID M0 <br />
Table 5-3: CPUID (CPUID, 0xE000-ED00) <br />
<br />
3:0 REVISION <br />
15:4 PARTNO : 0xC20 -M0 = Cortex<br />
19:16 CONSTANT :, 0xC -M = ARMv6<br />
23:20 - <br />
31:24 IMPLEMENTER : 0x41 = ARM<br />
5.3.3 <br />
(ICSR)<br />
<br />
Table 5-4: (ICSR,<br />
0xE000-ED04) <br />
<br />
5:0 VECTACTIVE RO :<br />
11:6 - - .<br />
0 = Thread <br />
0 =<br />
.<br />
: 16 CMSIS IRQ <br />
<br />
22 www.xinnovatech.com
XN62Lxxx<br />
17:12 VECTPENDING RO <br />
<br />
:<br />
21:18 - - .<br />
0 = <br />
0 =.<br />
22 ISRPENDING RO <br />
NMI :<br />
24:23 - - .<br />
0 = <br />
1 = <br />
.<br />
25 PENDSTCLR WO SysTick<br />
:<br />
0 = <br />
1 =<br />
<br />
26 PENDSTSET RW SysTick<br />
<br />
.<br />
:<br />
0 =<br />
1 = <br />
SysTick<br />
<br />
:<br />
0 =<br />
SysTick<br />
1 =<br />
SysTick<br />
.<br />
27 PENDSVCLR WO PendSV <br />
:<br />
0 =<br />
1 = PendSV .<br />
28 PENDSVSET RW PendSV <br />
.<br />
:<br />
0 =<br />
1 = PendSV <br />
<br />
:<br />
30:29 - - .<br />
0 = PendSV <br />
1 = PendSV <br />
.<br />
31 NMIPENDSET RW NMI <br />
.<br />
:<br />
0 =<br />
1 = NMI <br />
:<br />
0 = NMI <br />
1 = NMI <br />
<br />
NMI <br />
1 <br />
<br />
1 NMI <br />
www.xinnovatech.com 23
XN62Lxxx<br />
5.3.4 <br />
(AIRCR)<br />
<br />
Table 5-5: (AIRCR,<br />
0xE000-ED0C) <br />
0 - - .<br />
1 VECTCLRACTIVE WO <br />
0 CPU <br />
2 SYSRESETREQ WO :<br />
0 = <br />
14:3 - - <br />
1 = <br />
.<br />
15 ENDIANESS RO <br />
:<br />
0 = Little<br />
-endian<br />
1 = Big<br />
-endian.<br />
31:16 VECTKEY WO <br />
0x05FA VECTKEY <br />
<br />
5.3.5 <br />
(SCR)<br />
/<br />
<br />
Table 5-6: (SCR,<br />
0xE000- ED10) <br />
<br />
0 - <br />
1 SLEEPONEXIT <br />
Handler Thread <br />
0 = <br />
Thread 1 = (ISR)<br />
Thread 1 <br />
<br />
2 SLEEPDEEP :<br />
0 = <br />
3 - .<br />
1 = .<br />
4 SEVONPEND <br />
:<br />
31:5 - <br />
0 = <br />
1 = <br />
WFE <br />
WFESEV <br />
5.3.6 <br />
(CCR)<br />
<br />
Cortex-M0 <br />
24 www.xinnovatech.com
XN62Lxxx<br />
Table 5-7: (CCR,<br />
0xE000-ED14) <br />
<br />
2:0 - .<br />
3 UNALIGN_TRP 1<br />
HardFault 8:4 - .<br />
9 STKALIGN 1<br />
8 <br />
PSR [9]<br />
31:10 - .<br />
<br />
5.3.7 <br />
<br />
Cortex Microcontroller Software Interface Standard (CMSIS) SCB <br />
CMSIS <br />
SHPR2-SHPR3 .<br />
Table 5-8: SHPR2 ( 0xE000-ED1C) <br />
<br />
29:0 - .<br />
31:30 PRI_11 11 – SVCall <br />
“0” <br />
“3” <br />
Table 5-9: SHPR3 ( 0xE000-ED20) <br />
<br />
21:0 - .<br />
23:22 PRI_14 14 – PendSV <br />
29:24 - .<br />
“0” <br />
“3” <br />
31:30 PRI_15 15 – SysTick <br />
“0” <br />
“3” <br />
5.4 <br />
(NVIC)<br />
5.4.1 NVIC <br />
(NVIC<br />
)Cortex-M0 <br />
CPU <br />
• .<br />
• .<br />
• 32 .<br />
• .<br />
• .<br />
• (NMI).<br />
www.xinnovatech.com 25
XN62Lxxx<br />
<br />
1 <br />
Table 5-10: <br />
IRQ <br />
<br />
0x00 SP <br />
1 0x04 Reset -3 <br />
2 -14 0x08 NMI -2<br />
3 -13 0x0C HardFault -1<br />
10~4 0x10~0x28 <br />
11 -5 0x2C SVCall (1)<br />
13~12 0x30~0x34 <br />
14 -2 0x38 PendSV (1)<br />
15 -1 0x3C SysTick (1)<br />
16 0 0x40 0 (2) <br />
PIO0_0~PIO0_11 <br />
17 1 0x44 QSPI (2)<br />
18 2 0x48 <br />
19 3 0x4C <br />
20 4 0x50 PWM 0 <br />
(2)<br />
21 5 0x54 PWM 1 <br />
(2)<br />
22 6 0x58 PWM 2 <br />
(2)<br />
23 7 0x5C PWM2 (2)<br />
24 8 0x60 ADC1 (2) A/D <br />
25 9 0x64 ADC2 (2)<br />
26 10 0x68 UART 2 (2) (THRE)<br />
<br />
(THROE)<br />
(RBRS)<br />
(RBROE)<br />
27 11 0x6C UART 3 (2) (THRE)<br />
(THROE)<br />
(RBRS)<br />
(RBROE)<br />
28 12 0x70 TWS (2) TWS SI <br />
29 13 0x74 CT16B0 (2) 0~3<br />
0~1<br />
30 14 0x78 CT16B1 (2) 0~3<br />
0~1<br />
31 15 0x7C CT32B0 (2) 0~3<br />
0~3<br />
32 16 0x80 CT32B1 (2) 0~3<br />
26 www.xinnovatech.com
XN62Lxxx<br />
0~3<br />
33 17 0x84 SPI (2) Tx FIFO Rx FIFO <br />
Rx <br />
Rx <br />
34 18 0x88 UART0 (2) (THRE)<br />
(THROE)<br />
(RBRS)<br />
(RBROE)<br />
35 19 0x8C UART1 (2) (THRE)<br />
(THROE)<br />
(RBRS)<br />
(RBROE)<br />
36 20 0x90 (2) 0/1 <br />
37 21 0x94 ADC0 (2) A/D <br />
38 22 0x98 WDT (2) (WDINT)<br />
39 23 0x9C BOD (2) <br />
40 24 0xA0 PWM0 (2)<br />
41 25 0xA4 PIO0 (2) GPIO 0 <br />
42 26 0xA8 PIO1 (2) GPIO 1 <br />
43 27 0xAC PIO2 (2) GPIO 2 <br />
44 28 0xB0 PWM1 (2)<br />
45 29 0xB4 DMA (2) DMA <br />
46 30 0xB8 RTC (2) RTC <br />
47 31 0xBC DAC (2) D/A <br />
:<br />
(1) SCB SHPR2-SHPR3.<br />
(2) NVIC IPR0~IPR7.<br />
5.4.2 <br />
(NVIC)<br />
NVIC <br />
IRQ0~IRQ31, <br />
Table 5-11: NVIC <br />
<br />
INTNMI R/W 0x4004 8174 <br />
(NMI)<br />
0x00000000<br />
ISER R/W 0xE000 E100 0x00000000<br />
ICER R/W 0xE000 E180 0x00000000<br />
ISPR R/W 0xE000 E200 <br />
ICPR R/W 0xE000 E280 <br />
IPR0 R/W 0xE000 E400 <br />
IPR0<br />
IPR1 R/W 0xE000 E404 <br />
IPR1<br />
0x00000000<br />
0x00000000<br />
0x00000000<br />
0x00000000<br />
www.xinnovatech.com 27
XN62Lxxx<br />
IPR2 R/W 0xE000 E408 <br />
IPR2<br />
IPR3 R/W 0xE000 E40C <br />
IPR3<br />
IPR4 R/W 0xE000 E410 <br />
IPR4<br />
IPR5 R/W 0xE000 E414 <br />
IPR5<br />
IPR6 R/W 0xE000 E418 <br />
IPR6<br />
IPR7 R/W 0xE000 E41C <br />
IPR7<br />
0x00000000<br />
0x00000000<br />
0x00000000<br />
0x00000000<br />
0x00000000<br />
0x00000000<br />
5.4.3 <br />
(ISER)<br />
Table 5-12: (ISER,<br />
0xE000 E100) <br />
<br />
31:0 SETENA IRQ0~IRQ31 <br />
.<br />
0x00000000<br />
:<br />
0 = <br />
1 = <br />
:<br />
0 = <br />
1 = <br />
NVIC<br />
<br />
<br />
NVIC <br />
5.4.4 <br />
(ICER)<br />
<br />
Table 5-13: (ICE<br />
R, 0xE000 E180)<br />
<br />
31:0 CLRENA IRQ0~IRQ31 <br />
0x00000000<br />
:<br />
0 = <br />
1 = <br />
:<br />
0 = <br />
1 = <br />
5.4.5 <br />
(ISPR)<br />
<br />
Table 5-14: <br />
(ISPR, 0xE000 E200) <br />
<br />
28 www.xinnovatech.com
XN62Lxxx<br />
31:0 SETPEND IRQ0~IRQ31 .<br />
0x00000000<br />
:<br />
0 = <br />
1 =<br />
:<br />
0 = <br />
1 = <br />
5.4.6 <br />
(ICPR)<br />
<br />
Table 5-15: (<br />
(ICPR, 0xE000 E280) <br />
<br />
31:0 CLRPEND IRQ0~IRQ31 <br />
.<br />
0x00000000<br />
:<br />
0 = <br />
1 = <br />
<br />
:<br />
0 = <br />
1 = <br />
5.4.7 <br />
<br />
IPR0-IPR7 <br />
(IRQ0~IRQ31)2 4 <br />
4 31 24 23 16 15 8 7 0<br />
IPR7<br />
PRI_31 PRI_30 PRI_29 PRI_28<br />
.<br />
.<br />
.<br />
.<br />
.<br />
.<br />
IPRn<br />
PRI_(4n+3) PRI_(4n+2) PRI_(4n+1) PRI_(4n)<br />
.<br />
.<br />
.<br />
.<br />
.<br />
.<br />
IPR0<br />
PRI_3 PRI_2 PRI_1 PRI_0<br />
Figure 5-3: IPR <br />
Table 5-16: IPRn (IPR0~7, 0xE000 E400~0xE000 E41C) <br />
<br />
7:0 , 0 <br />
7 6<br />
0x00<br />
15:8 , 1 <br />
0-3.<br />
0x00<br />
23:16 , 2 <br />
0x00<br />
31:24 , 3 5~0 0<br />
0x00<br />
www.xinnovatech.com 29
XN62Lxxx<br />
<br />
M IPR :<br />
• IPR , N, N = M DIV 4<br />
• IPR <br />
M MOD 4, :<br />
– 0 <br />
7:0<br />
– 1 <br />
15:8<br />
– 2 <br />
23:16<br />
– 3 <br />
31:24<br />
5.4.7.1 NMI <br />
<br />
ARM Cortex-M0 (NMI).<br />
Table 5-17: NMI (INTNMI,<br />
0x4004 8174)<br />
<br />
5:0 NMISRC NMI <br />
. -<br />
0 ~ 3 wake<br />
-up 0~3<br />
4 PWM 0 <br />
5 PWM 1 <br />
6 PWM 2 <br />
7 PWM2<br />
8 ADC1<br />
9 ADC2<br />
10 UART2<br />
11 UART3<br />
12 TWS<br />
13 CT16B0<br />
14 CT16B1<br />
15 CT32B0<br />
16 CT32B1<br />
17 SPI<br />
18 UART0<br />
19 UART1<br />
20 <br />
21 ADC0<br />
22 WDT<br />
23 BOD<br />
24 PWM0<br />
25 PIO0<br />
26 PIO1<br />
27 PIO2<br />
30 www.xinnovatech.com
XN62Lxxx<br />
28 PWM1<br />
29 DMA<br />
30 RTC<br />
31 DAC<br />
32~62 <br />
63 NMI <br />
31:6 - - 0x0<br />
5.5 <br />
(SysTick)<br />
Cortex-M0 <br />
10 <br />
<br />
Cortex-M0 <br />
Cortex-M0 <br />
• RTOS<br />
100Hz<br />
(SysTick)<br />
• .<br />
• <br />
• / <br />
COUNTFLAG<br />
<br />
<br />
• 24<br />
• <br />
• <br />
Table 5-18: <br />
( 0xE000 E000)<br />
<br />
SYST_CSR R/W 0x010 0x0000 0000<br />
SYST_RVR R/W 0x014 <br />
0x0000 0000<br />
SYST_CVR R/W 0x018 <br />
0x0000 0000<br />
5.5.1 <br />
<br />
Cortex-M0 Table 5-18: <br />
(SYST_CSR - 0xE000 E010) <br />
<br />
0 ENABLE 0<br />
0 <br />
1 <br />
1 TICKINT 0<br />
0 <br />
1 <br />
www.xinnovatech.com 31
XN62Lxxx<br />
15:2 - . NA<br />
16 COUNTFLAG - <br />
0 1 0<br />
31:17 - - NA<br />
5.5.2 <br />
<br />
0 <br />
Table 5-19: (SYST_RVR<br />
- 0xE000 E014) <br />
<br />
23:0 RELOAD <br />
0 0<br />
31:24 - NA<br />
5.5.3 <br />
<br />
Table 5-20: (SYST_CVR<br />
- 0xE000 E018) <br />
23:0 CURRENT <br />
0<br />
<br />
STCTRL COUNTFLAG 31:24 NA<br />
5.5.4 <br />
<br />
24 <br />
0 10ms <br />
CPU SYST<br />
CPU 20Mhz10ms<br />
:<br />
1. SYST_RVR RELOAD <br />
RELOAD = (<br />
× 10 ms) −1<br />
= (20MHz ×10 ms) −1<br />
= 200000−1<br />
= 199999<br />
= 0x00030D3F<br />
2. SYST_CVR <br />
3. SYST_SCR 0x7<br />
5.6 <br />
XN62L <br />
• <br />
32 www.xinnovatech.com
XN62Lxxx<br />
• <br />
• <br />
• <br />
• <br />
Table 5-21: <br />
<br />
PMUBase:0x4003 8000<br />
PCON R/W 0x000 0x0000 0000<br />
GPREG0 R/W 0x004 0 0x0000 0000<br />
GPREG1 R/W 0x008 1 0x0000 0000<br />
GPREG2 R/W 0x00C 2 0x0000 0000<br />
GPREG3 R/W 0x010 3 0x0000 0000<br />
SYSCFG R/W 0x014 <br />
(RTC WAKEUP 0x0000 0000<br />
Base:0x4004 8000<br />
)<br />
SYSMEMREMAP R/W 0x000 0x0000 0000<br />
PRESETCTRL R/W 0x004 0x000F FFFF<br />
SYSPLLCTRL R/W 0x008 PLL 0x0000 0000<br />
SYSPLLSTAT R 0x00C PLL 0x0000 0000<br />
- - 0x010 - 0x01C -<br />
SYSOSCCTRL R/W 0x020 <br />
0x0000 0000<br />
WDTOSCCTRL R/W 0x024 <br />
0x0000 0000<br />
IRCCTRL R/W 0x028 IRC<br />
0x0000 0080<br />
- - 0x02C -<br />
SYSRESSTAT R/W 0x030 0x0000 0000<br />
- - 0x034 - 0x03C -<br />
SYSPLLCLKSEL R/W 0x040 PLL <br />
0x0000 0000<br />
SYSPLLCLKUEN R/W 0x044 PLL <br />
0x0000 0000<br />
- - 0x048 - 0x06C -<br />
MAINCLKSEL R/W 0x070 0x0000 0000<br />
MAINCLKUEN R/W 0x074 <br />
0x0000 0000<br />
SYSAHBCLKDIV R/W 0x078 AHB 0x0000 0001<br />
- - 0x07C -<br />
SYSAHBCLKCTRL R/W 0x080 AHB <br />
0xFFFF FFFF<br />
- - 0x084 - 0x094 -<br />
UART0CLKDIV R/W 0x098 UART0 0x0000 0000<br />
UART1CLKDIV R/W 0x09C UART1 0x0000 0000<br />
- - 0x0A0- 0x0DC -<br />
CLKOUTCLKSEL R/W 0x0E0 CLKOUT 0x0000 0000<br />
www.xinnovatech.com 33
XN62Lxxx<br />
CLKOUTUEN R/W 0x0E4 CLKOUT <br />
0x0000 0000<br />
CLKOUTDIV R/W 0x0E8 CLKOUT 0x0000 0000<br />
- - 0x0EC -0x0FC -<br />
PIOPORCAP0 R 0x100 PIO 0 <br />
PIOPORCAP1 R 0x104 PIO 1 <br />
PIOPORCAP2 R 0x108 PIO 2 <br />
- - 0x 10C - 0x130 -<br />
IOCONFIGCLKDIV6 R/W 0x134 IO 6 0x0000 0000<br />
IOCONFIGCLKDIV5 R/W 0x138 IO 5 0x0000 0000<br />
IOCONFIGCLKDIV4 R/W 0x13C IO 4 0x0000 0000<br />
IOCONFIGCLKDIV3 R/W 0x140 IO 3 0x0000 0000<br />
IOCONFIGCLKDIV2 R/W 0x144 IO 2 0x0000 0000<br />
IOCONFIGCLKDIV1 R/W 0x148 IO 1 0x0000 0000<br />
IOCONFIGCLKDIV0 R/W 0x14C IO 0 0x0000 0000<br />
BODCTRL R/W 0x150 BOD 0x0000 0000<br />
- - 0x154 - 0x1FC -<br />
DSWAKECTL R/W 0x200 0x0000 0000<br />
DSWAKEEN R/W 0x204 <br />
0x0000 0000<br />
DSWAKECLR W 0x208 <br />
0x0000 0000<br />
DSWAKE R 0x20C 0x0000 0000<br />
- - 0x210 - 0x22C -<br />
PDSLEEPCFG R/W 0x230 <br />
0x0000 0003<br />
PDAWAKECFG R/W 0x234 <br />
0x0000 EFF0<br />
PDRUNCFG R/W 0x238 0x0000 0000<br />
- - 0x22C <br />
UART2CLKDIV R/W 0x240 UART2 0x0000 0000<br />
UART3CLKDIV R/W 0x244 UART3 0x0000 0000<br />
SYSAHBCLKCTRL PDRUNCFG <br />
bootloader <br />
5.6.1 <br />
:<br />
• (POR)<br />
• RESET#<br />
• <br />
• <br />
(BOD)<br />
• <br />
• <br />
34 www.xinnovatech.com
XN62Lxxx<br />
RESET#Schmitt <br />
trigger <br />
15us <br />
IRC <br />
PORBOD<br />
• IRC<br />
IRC <br />
• ROM <br />
<br />
0 <br />
5.6.1.1 <br />
F<br />
lash SRAM ARM <br />
Table 5-22: (<br />
SYSMEMREMAP, 0x4004 8000) <br />
<br />
1:0 MAP 00<br />
0x0<br />
0x1<br />
0x2<br />
<br />
<br />
SRAM <br />
<br />
SRAM Flash <br />
Flash 0 31:2 - - 0x00<br />
5.6.1.2 <br />
SYSRSTSTAT<br />
<br />
1 POR <br />
0<br />
EXTRST POR <br />
Table 5-23: (SYSRESSTAT,<br />
0x4004 8030) <br />
<br />
0 POR POR 0<br />
0 POR <br />
1 POR <br />
1 EXTRST 0<br />
0 RESET <br />
1 RESET <br />
2 WDT 0<br />
0 WDT <br />
1 WDT <br />
3 BOD BOD 0<br />
0 BOD <br />
1 BOD <br />
4 SYSRST <br />
<br />
RESET# 0<br />
0 <br />
www.xinnovatech.com 35
XN62Lxxx<br />
1 <br />
31:5 - - 0x00<br />
5.6.1.3 PIO POR<br />
PIO POR <br />
3 PIOPORCAP0 PIO 0 <br />
Table 5-24: <br />
0 (PIOPORCAP0, 0x4004 8100) <br />
<br />
31:0 PIO0_STAT PIO0_0 ~ PIO0_31 <br />
<br />
PIOPORCAP1 PIO 1 <br />
Table 5-25: <br />
1 (PIOPORCAP1, 0x4004 8104) <br />
<br />
6:0 PIO1_STAT PIO1_0 ~ PIO1_6 <br />
<br />
31:7 - NA<br />
PIOPORCAP2 PIO 2 <br />
Table 5-26: <br />
2 (PIOPORCAP2, 0x4004 8108) <br />
<br />
15:0 PIO2_STAT PIO2_0 ~ PIO2_15 <br />
<br />
31:16 - NA<br />
5.6.1.4 <br />
<br />
AIRCR SYSRESETREQ <br />
SCB 5.6.1.5 POR<br />
POR<br />
<br />
POR Cortex-M0 <br />
5.6.1.6 BOD<br />
BOD<br />
<br />
1. <br />
2.624V <br />
0.135V<br />
2. BOD <br />
2.828V <br />
0.101V<br />
Table 5-27: BOD (BODCTRL, 0x4004 8150)<br />
<br />
3:0 - - 0x0<br />
4 BODRSTEN BOD 0<br />
0 BOD <br />
1 BOD <br />
36 www.xinnovatech.com
XN62Lxxx<br />
5 - - 0x0<br />
6 BODINTCLR - 1 BOD <br />
NA<br />
31:5 - - 0x0<br />
5.6.2 <br />
5.6.2.1 <br />
MCU XN62L <br />
<br />
XN62L <br />
XTALIN<br />
XTALOUT<br />
SYS_OSC<br />
SYS_OSC_CLK<br />
SYS_PLLCLK_IN<br />
PLL<br />
System AHB<br />
CLK DIVIDER<br />
System Clk<br />
ARM Core<br />
Peripheral<br />
PCLK<br />
SYS_OSC_BYPASS<br />
SYS_PLLCLKIN_SEL<br />
MAIN_CLK<br />
IRC_OSC<br />
IRC_OSC_CLK<br />
MAINCLK_SEL<br />
SYSAHBCLKCTRL<br />
WDT_CLK<br />
WDT_OSC<br />
WDT_OSC_CLK<br />
WDT_CLK_SEL<br />
INTERNAL<br />
CLOCK<br />
DIVIDERS<br />
UART0/1,<br />
RTC,<br />
SysTick<br />
PCLK<br />
RTCXIN<br />
RTCXOUT<br />
RTC_OSC<br />
1Hz<br />
1KHz<br />
RTC<br />
Timer<br />
RTC<br />
DIVIDER<br />
RTC_SEL<br />
CLOCKOUT<br />
DIVIDER<br />
CLOCKOUT<br />
Outside-Chip-Inside<br />
CLOCKOUT_SEL<br />
Inside-Chip-Outside<br />
Figure 5-4: <br />
<br />
XN62L IRC <br />
<br />
SYSAHBCLKCTRL UART0/1<br />
/2/3 <br />
lock<br />
<br />
WDT main main clock IRC<br />
clock<br />
<br />
CLKOUT <br />
5.6.2.2 <br />
<br />
www.xinnovatech.com 37
XN62Lxxx<br />
Table 5-28: <br />
(SYSOSCCTRL, 0x4004 8020) <br />
<br />
0 BYPASS 0<br />
0 <br />
1 <br />
PLL (sys_osc_clk) XTALIN<br />
<br />
1 FREQRANGE 0<br />
0 0.4 - 3MHz <br />
1 3 - 16MHz <br />
31:2 - 0x00<br />
5.6.2.3 <br />
<br />
<br />
<br />
clkana)<br />
(F<br />
clkana)<br />
WDT_CLK (F<br />
clkana) FRWQSEL 320KHz 2.2MHz<br />
<br />
DIVSEL <br />
WDT_CLK<br />
<br />
WDT_CLK = F clkana/(4 × (1 + DIVSEL)) = 1.25K Hz ~ 550K Hz ().<br />
: FREQSEL F clkana ±<br />
20% <br />
<br />
IRC <br />
:<br />
Table 5-29: (WDTOSCCTRL,<br />
0x4004 8024) <br />
<br />
4:0 DIVSEL F clkana <br />
0x0<br />
8:5 FREQSEL <br />
(F clkana). 0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
0x8<br />
0x9<br />
0xA<br />
0xB<br />
0xC<br />
0xD<br />
0xE<br />
0xF<br />
0.32Hz<br />
0.6MHz<br />
0.85MHz<br />
1.04MHz<br />
1.16MHz<br />
1.28MHz<br />
1.43MHz<br />
1.52MHz<br />
1.63MHz<br />
1.7MHz<br />
1.8MHz<br />
1.92MHz<br />
2MHz<br />
2.08MHz<br />
2.2MHz<br />
38 www.xinnovatech.com
XN62Lxxx<br />
31:9 - - 0x0<br />
5.6.2.4 <br />
<br />
20MHz <br />
Table 5-30: (IRCCTRL,<br />
0x4004 8028) <br />
9:0 TRIM 0xxxx<br />
31:10 - 0x00<br />
5.6.2.5 <br />
PLL<br />
XN62L PLL<br />
<br />
M[7:0]<br />
VCO_OUT<br />
FIN<br />
FCK<br />
UP<br />
VCTR<br />
N[6:0] PFD CP VCO ODSEL[1:0]<br />
RCK<br />
DN<br />
FOUT<br />
UP<br />
DN<br />
LKDT<br />
LKDT<br />
Figure 5-5: PLL <br />
PLL<br />
FIN <br />
2MHz 50MHz<br />
PFD<br />
/<br />
<br />
(VCO)<br />
VCO<br />
<br />
12.5 MHz 500 MHz<br />
2xOD <br />
M<br />
PLL <br />
<br />
OD M PLL <br />
FOUT 100 MHz<br />
(LKDT)<br />
<br />
” <br />
<br />
<br />
<br />
<br />
PLL PLL<br />
<br />
SYSPLL_PD 1 <br />
www.xinnovatech.com 39
XN62Lxxx<br />
<br />
PLL <br />
SYSPLL_PD 0 PLL<br />
<br />
<br />
<br />
• <br />
<br />
ODSEL <br />
ODSEL 2 OD <br />
50%<br />
• <br />
<br />
M PLL <br />
M 1PLL <br />
<br />
• <br />
PLL <br />
M ODSEL <br />
<br />
PLL PLL <br />
<br />
PLL :<br />
Table 5-31: PLL <br />
<br />
FIN<br />
VCO<br />
FOUT<br />
OD<br />
M<br />
N<br />
PLL<br />
PLL <br />
sys_pllclkin SYSPLLCLKSEL <br />
(VCO); 12.5MHz 500MHz.<br />
PLL <br />
sys_pllclkout. FOUT100MHz.<br />
PLL <br />
SYSPLLCTRL ODSEL <br />
PLL SYSPLLCTRL<br />
M <br />
SYSPLLCTRL N<br />
PLL<br />
50%<br />
FOUT=FIN X<br />
M<br />
N<br />
X<br />
1<br />
OD<br />
=<br />
VCD<br />
2 X OD<br />
<br />
MOD<br />
1. FIN<br />
2. M<br />
M = FOUT / FIN <br />
3. VCO = 2 × OD × FOUT.<br />
4. <br />
5. FOUT 100MHz.<br />
Table 5-32: PLL <br />
PLL (FIN)<br />
(FOUT) N M ODSEL<br />
(<br />
OD) VCO <br />
12MHz 24MHz 1 8 10 () 4 192MHz<br />
40 www.xinnovatech.com
XN62Lxxx<br />
12MHz 50MHz 6 100 01 () 2 200MHz<br />
5.6.2.5.1 PLL<br />
<br />
PLL <br />
PLL <br />
2MHz 20MHz PLL <br />
CPU<br />
Table 5-33: PLL (SYSPLLCTRL, 0x4004 8008) <br />
<br />
7:0 M <br />
2M255<br />
14:8 N <br />
1N127<br />
0x0<br />
0x0<br />
16:15 ODSEL <br />
OD 00<br />
0x0 OD = 1<br />
0x1 OD = 2<br />
0x2 OD = 4<br />
0x3 OD = 8<br />
31:17 - 0x0<br />
5.6.2.5.2 PLL<br />
<br />
PLL Table 5-34: PLL (SYSPLLSTAT, 0x4004 800C) <br />
<br />
0 LOCK PLL 0<br />
0 PLL <br />
1 PLL <br />
31:1 - - 0x00<br />
5.6.2.5.3 PLL<br />
<br />
PLL <br />
SYSPLLCLKUEN <br />
PLL <br />
Table 5-35: PLL <br />
(SYSPLLCLKSEL, 0x4004 8040) <br />
<br />
1:0 SEL PLL 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
IRC<br />
<br />
<br />
<br />
31:2 - - 0x00<br />
5.6.2.5.4 PLL<br />
<br />
SYSPLLCLKSEL <br />
SYSPLLUEN 0 1<br />
www.xinnovatech.com 41
XN62Lxxx<br />
Table 5-36: PLL <br />
(SYSPLLCLKUEN, 0x4004 8044) <br />
<br />
0 ENA PLL 0<br />
0 <br />
1 PLL <br />
31:1 - - 0x00<br />
5.6.2.6 <br />
5.6.2.6.1 <br />
<br />
PLL <br />
<br />
MAINCLKUEN 0 1 <br />
Table 5-37: <br />
(MAINCLKSEL, 0x4004 8070) <br />
<br />
1:0 SEL 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
PLL <br />
<br />
PLL <br />
31:2 - - 0x00<br />
5.6.2.6.2 <br />
<br />
MAINCLKSEL <br />
MAINCLKUEN 0 1<br />
Table 5-38: (MAINC<br />
LKUEN, 0x4004 8074) <br />
<br />
0 ENA 0<br />
0 <br />
1 <br />
31:1 - - 0x00<br />
5.6.2.7 AHB<br />
5.6.2.7.1 AHB<br />
<br />
DIV 0 Table 5-39: AHB (SYSA<br />
HBCLKDIV, 0x4004 8078) <br />
<br />
42 www.xinnovatech.com
XN62Lxxx<br />
7:0 DIV AHB <br />
0 0x01<br />
1: 1.<br />
<br />
255: 255.<br />
31:8 0x00<br />
5.6.2.7.2 AHB<br />
AHBCLKCTRL <br />
0 AHB<br />
APB AHB ARM Cortex-M0 SYSCON PMU<br />
<br />
bootloader<br />
<br />
Table 5-40: AHB (SYSAHBCLKCTRL,<br />
0x4004 8080) <br />
<br />
0 SYS AHB APB AHB ARM Cortex-M0 SYSCON 1<br />
0 <br />
1 <br />
PMU<br />
1 - NA<br />
2 RAM RAM . 1<br />
0 <br />
1 <br />
4:3 - - NA<br />
5 TWS TWS 1<br />
0 <br />
1 <br />
6 XDSP xDSP 1<br />
0 <br />
1 <br />
7 CT16B0 16 0 1<br />
0 <br />
1 <br />
8 CT16B1 16 1 1<br />
0 <br />
1 <br />
9 CT32B0 32 0 1<br />
0 <br />
1 <br />
10 CT32B1 32 1 1<br />
0 <br />
1 <br />
11 SPI SPI 1<br />
www.xinnovatech.com 43
XN62Lxxx<br />
0 <br />
1 <br />
12 UART0 UART0 1<br />
0 <br />
1 <br />
13 UART1 UART1 1<br />
0 <br />
1 <br />
14 ADC0 TWS 1<br />
0 <br />
1 <br />
15 WDT WDT 1<br />
0 <br />
1 <br />
16 IOCON IO 1<br />
0 <br />
1 <br />
17 DMA DMA 1<br />
0 <br />
1 <br />
18 QSPI QSPI 1<br />
0 <br />
1 <br />
19 RTC RTC 1<br />
0 <br />
1 <br />
20 CMP 1<br />
0 <br />
1 <br />
21 PWM0 PWM0 1<br />
0 <br />
1 <br />
22 PWM1 PWM1 1<br />
0 <br />
1 <br />
23 PWM2 PWM2 1<br />
0 <br />
1 <br />
24 ADC1 ADC1 1<br />
0 <br />
44 www.xinnovatech.com
XN62Lxxx<br />
1 <br />
25 ADC2 ADC2 1<br />
0 <br />
1 <br />
26 DAC DAC 1<br />
0 <br />
1 <br />
27 UART2 UART2 1<br />
0 <br />
1 <br />
28 UART3 UART3 1<br />
0 <br />
1 <br />
29 GPIO0 GPIO0 1<br />
0 <br />
1 <br />
30 GPIO1 GPIO1 1<br />
0 <br />
1 <br />
31 GPIO2 GPIO2 1<br />
0 <br />
1 <br />
5.6.2.8 UART <br />
UART <br />
UART0/1/2/3 <br />
UARTn_PCLK DIV 0 <br />
Table 5-41: UARTn <br />
(UART0CLKDIV, 0x4004 8098; UART1CLKDIV, 0x4004 809C; UART2CLKDIV, <br />
0x4004 8240; UART3CLKDIV, 0x4004 8244) <br />
<br />
7:0 DIV UARTn 0x0<br />
0x00<br />
0x01<br />
UARTn <br />
1<br />
~ ~<br />
0xFF<br />
255.<br />
31:8 - 0x00<br />
5.6.2.9 CLKOUT<br />
5.6.2.9.1 CLKOUT <br />
<br />
CLKOUT clkout_clk IRC<br />
WDT<br />
RTC clkout_clk CLKOUTCLKUEN <br />
www.xinnovatech.com 45
XN62Lxxx<br />
Table 5-42: CLKOUT <br />
(CLKOUTCLKSEL, 0x4004 80E0) <br />
<br />
1:0 SEL CLKOUT 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
IRC <br />
<br />
<br />
<br />
RTC <br />
31:2 - - 0x00<br />
5.6.2.9.2 CLKOUT<br />
<br />
CLKOUTCLKSEL <br />
CLKCLKUEN 0 1<br />
Table 5-43: CLKOUT (CLKOUTUEN,<br />
0x4004 80E4) <br />
<br />
0 ENA CLKOUT 0<br />
0 <br />
1 <br />
31:1 - - 0x00<br />
5.6.2.9.3 CLKOUT<br />
<br />
CLKOUT clkout_clk <br />
Table 5-44: CLKOUT <br />
(CLKOUTDIV, 0x4004 80E8) <br />
<br />
7:0 DIV 0<br />
0x00<br />
0x01<br />
<br />
1<br />
~ ~<br />
0xFF<br />
255.<br />
31:8 - - 0x00<br />
5.6.2.10 <br />
7 <br />
IO <br />
DIV 0 Table 5-45: IOCONFIG <br />
0 ~ 6(IOCONFIGCLKDIV0 ~ IOCONFIGCLKDIV6, 4004 8014C 4004 80134) <br />
<br />
7:0 DIV <br />
1~255 0<br />
0x00<br />
<br />
46 www.xinnovatech.com
XN62Lxxx<br />
0x01<br />
0x03<br />
~<br />
0xFF<br />
1<br />
3<br />
~<br />
255<br />
31:8 - - 0x00<br />
5.6.3 <br />
XN62L <br />
<br />
<br />
<br />
SWD<br />
<br />
Table 5-46: <br />
<br />
<br />
M0 - <br />
SRAM - <br />
FLASH - <br />
IRCOUT - PDRUNCFG - PDRUNCFG - - <br />
IRC - PDRUNCFG - PDRUNCFG - - <br />
BOD - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - <br />
ADC0 - PDRUNCFG - PDRUNCFG - - <br />
DAC - PDRUNCFG - PDRUNCFG - - <br />
SYSOSC - PDRUNCFG - PDRUNCFG - - <br />
WDTOSC - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - <br />
SYSPLL - PDRUNCFG - PDRUNCFG - - <br />
ADC1 - PDRUNCFG - PDRUNCFG - - <br />
ADC2 - PDRUNCFG - PDRUNCFG - - <br />
RTCOSC - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - PDRUNCFG<br />
COMP - PDRUNCFG - PDRUNCFG - - <br />
TWS AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
xDSP AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
CT16B0 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
CT16B1 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
CT32B0 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
CT32B1 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
SPI AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
UART0,1,<br />
AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
2,3<br />
ADC0,1,2<br />
AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
/DAC<br />
WDT AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
www.xinnovatech.com 47
XN62Lxxx<br />
IOCON AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
DMA AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
RTC AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
CMP AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
<br />
PWM0,1,2 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
GPIO0 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
GPIO1 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
GPIO2 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - <br />
WAKEUP - - - - - - - <br />
5.6.3.1 <br />
<br />
ARM Cortex-M0 <br />
<br />
<br />
Table 5-47:<br />
(PCON, 0x4003 8000) <br />
<br />
0 - - . 0<br />
1 DPDEN 0<br />
0 ARM WFI <br />
ARM Cortex-M0 <br />
1 ARM WFI <br />
7:2 - - . 0x0<br />
8 SLEEPFLAG 0<br />
0 : <br />
: .<br />
1 : <br />
: 1 SLEEPFLAG <br />
10:9 - - . 00<br />
11 DPDFLAG 0<br />
0 : <br />
: .<br />
1 : <br />
: <br />
31:12 - - . 0x0<br />
5.6.3.2 <br />
0~3<br />
V<br />
DD(3V3) <br />
Table 5-48: <br />
0 ~3 (GPREG0 - GPREG3, 0x4003 8004 ~ 0x4003 8010) <br />
<br />
31:0 GPDATA 0x0<br />
48 www.xinnovatech.com
XN62Lxxx<br />
5.6.3.3 RTC<br />
<br />
RTC 32 1 kHz RTC<br />
1kHz <br />
Hz<br />
RTC <br />
RTC RTC <br />
RTC <br />
SYSAHBCLKCTRL <br />
RTC<br />
<br />
Table 5-49: (SYSCFG,<br />
0x4003 8014) <br />
<br />
10:0 - - . 0x0<br />
12:11 RTCCLK RTC 0000<br />
00 1 Hz <br />
01 IRC <br />
10 1 kHz <br />
11 RTC PCLK<br />
31:15 - - . 0x0<br />
5.6.3.4 <br />
<br />
RTC BOD (WD<br />
T) BOD <br />
WDT WDMODE WDLOCKCLK <br />
Table 5-50: (PDSLEEPCFG,<br />
0x4004 8230) <br />
<br />
2:0 - . 011<br />
3 BOD_PD <br />
BOD 0<br />
0 <br />
1 <br />
5:4 - . 00<br />
6 WDTOSC_PD <br />
WDMODE 0<br />
0 <br />
1 <br />
WDLOCKCLK 1 <br />
11:7 - - 00000<br />
12 RTCOSC_PD <br />
RTC 0<br />
0 <br />
1 <br />
15:13 - - 00<br />
31:16 - - 0x00<br />
5.6.3.5 <br />
<br />
Table 5-51: (PDAWAKECFG,<br />
0x4004 8234) <br />
www.xinnovatech.com 49
XN62Lxxx<br />
<br />
0 IRCOUT_PD IRC 0<br />
0 <br />
1 <br />
1 IRC_PD IRC 0<br />
0 <br />
1 <br />
2 - - 0<br />
3 BOD_PD BOD 0<br />
0 <br />
1 <br />
4 ADC0_PD ADC0 1<br />
0 <br />
1 <br />
5 SYSOSC_PD 1<br />
0 <br />
1 <br />
6 WDTOSC_PD <br />
1<br />
0 <br />
1 <br />
7 SYSPLL_PD PLL 1<br />
0 <br />
1 <br />
8 - - 1<br />
9 ADC1_PD ADC1 1<br />
0 <br />
1 <br />
10 ADC2_PD ADC2 1<br />
0 <br />
1 <br />
11 DAC_PD DAC 1<br />
0 <br />
1 <br />
12 RTCOSC_PD RTC 0<br />
0 <br />
1 <br />
14:13 - - 11<br />
15 COMP_PD 1<br />
0 <br />
50 www.xinnovatech.com
XN62Lxxx<br />
1 <br />
31:16 - - 0<br />
5.6.3.6 <br />
PDRUNCFG <br />
<br />
bootloader : 2 <br />
WDT <br />
• <br />
WDT <br />
MOD <br />
5<br />
PDRUNCFG 6 <br />
.<br />
• IRC WDT <br />
MOD <br />
5<br />
PDRUNCFG 0 1 .<br />
Table 5-52: (PDRUNCFG<br />
, 0x4004 8238) <br />
<br />
0 IRCOUT_PD IRC 0<br />
0 <br />
1 <br />
1 IRC_PD IRC 0<br />
0 <br />
1 <br />
2 - - 0<br />
3 BOD_PD BOD 0<br />
0 <br />
1 <br />
4 ADC0_PD ADC0 0<br />
0 <br />
1 <br />
5 SYSOSC_PD 0<br />
0 <br />
1 <br />
6 WDTOSC_PD 0<br />
0 <br />
1 <br />
7 SYSPLL_PD PLL 0<br />
0 <br />
1 <br />
8 - - 0<br />
9 ADC1_PD ADC1 0<br />
0 <br />
1 <br />
10 ADC2_PD ADC2 0<br />
www.xinnovatech.com 51
XN62Lxxx<br />
0 <br />
1 <br />
11 DAC_PD DAC 0<br />
0 <br />
1 <br />
12 RTCOSC_PD RTC 0<br />
0 <br />
1 <br />
14:13 - - 00<br />
15 COMP_PD 0<br />
0 <br />
1 <br />
31:16 - - 0<br />
5.6.3.7 <br />
<br />
ARM Cortex-M0 system clock<br />
<br />
PDRUNCFG SYSAHBCLKCTRL <br />
PDRUNCFG<br />
SYSAHBCLKCTRL <br />
<br />
• SYSAHBCLKCTRL<br />
• PDRUNCFGPLL<br />
ADCBOD<br />
,<br />
• system clockIRC<br />
• system clockSYSPLLCTRL<br />
SYSAHBCLKDIV<br />
• (UART0/1 /2/3, WDT)<br />
<br />
5.6.3.8 <br />
ARM -M0 <br />
Cortex<br />
<br />
<br />
<br />
SYSAHBCLKCTRL <br />
<br />
<br />
<br />
<br />
• <br />
• system clock<br />
• <br />
<br />
52 www.xinnovatech.com
XN62Lxxx<br />
<br />
1. <br />
PCON DPDEN 0<br />
2. ARM Cortex-M0 SCR SLEEPDEEP 0<br />
3. ARM Cortex-M0 Wait-For-Interrupt (WFI) <br />
<br />
<br />
PDRUNCFG SYSAHBCLKDIV <br />
<br />
5.6.3.9 <br />
system BOD<br />
clock<br />
RTC <br />
BOD<br />
RTC <br />
PDSLEEPCFG RTC<br />
<br />
<br />
RTC <br />
<br />
<br />
<br />
PDSLEEPCFG :<br />
• RTC <br />
<br />
IRC<br />
PLL <br />
• BOD <br />
• SYSAHBCLKCTRL<br />
WDT <br />
• RTC RTC <br />
<br />
<br />
1. <br />
PCON DPDEN 0<br />
2. PDSLEEPCFG .<br />
3. <br />
PDAWAKECFG.<br />
4. <br />
– <br />
NVIC – RTC NVIC RTC <br />
5. <br />
MAINCLKSEL <br />
6.SYSAHBCLKCTRL <br />
RTC WDT <br />
7. ARM Cortex-M0 SCR SLEEPDEEP 1<br />
8. ARM Cortex-M0 Wait-For-Interrupt (WFI) <br />
<br />
<br />
www.xinnovatech.com 53
XN62Lxxx<br />
• PIO0_0<br />
~ PIO0_11 <br />
• RTC <br />
• <br />
• BOD <br />
BOD <br />
PDSLEEPCFG BOD BODCTRL <br />
• <br />
PDSLEEPCFG SYSAHBCLKCTRL WDT <br />
• Reset<br />
<br />
ARM <br />
PIO0_0 ~ PIO0_11 <br />
<br />
<br />
NVIC <br />
0 3 PIO0_0 PIO0_11 <br />
<br />
RTC <br />
RTC RTC NVIC<br />
RTC <br />
5.6.3.10 <br />
<br />
WAKEUP <br />
WDMODE WDLOCKDP 1 <br />
<br />
RTC<br />
RTC <br />
RTC<br />
RTC<br />
<br />
PMU 4 32 <br />
SRAM <br />
<br />
WAKEUP .<br />
<br />
<br />
RTC RTC <br />
WAKEUP <br />
RTC RTC <br />
<br />
WDMODE <br />
WDLOCKDP 0 <br />
WDLOCKDP = 1<br />
<br />
<br />
1. PCON<br />
DPDEN1<br />
2. <br />
3. ARM Cortex-M0 SCRSLEEPDEEP1<br />
4. ARM Cortex -M0 Wait-For-Interrupt (WFI) <br />
<br />
54 www.xinnovatech.com
XN62Lxxx<br />
<br />
RTC <br />
XN62L <br />
• WAKEUP XN62L<br />
WAKEUP <br />
WAKEUP <br />
WAKEUP <br />
1. WAKEUP<br />
– PMU <br />
– GPREG0 GPREG3 <br />
– RTC RTC <br />
2. PCON<br />
<br />
3. PCON .<br />
4. <br />
5. PMU<br />
5.6.4 <br />
XN62L <br />
5.6.4.1 <br />
DSWAKECTL P0 PIO0_0 ~ PIO0_11 <br />
DSWAKECTL<br />
0 11 PIO0_0 ~ PIO0_11 <br />
Table 5-53:(DSWAKECTL,<br />
0x4004 8200) <br />
<br />
0 CTLPIO0_0 PIO0_0 <br />
0<br />
0 =<br />
1 =<br />
1 CTLPIO0_1 PIO0_1 <br />
0<br />
0 =<br />
1 =<br />
2 CTLPIO0_2 PIO0_2 <br />
0<br />
0 =<br />
1 =<br />
3 CTLPIO0_3 PIO0_3 <br />
0<br />
0 =<br />
1 =<br />
www.xinnovatech.com 55
XN62Lxxx<br />
4 CTLPIO0_4 PIO0_4 <br />
0<br />
0 =<br />
1 =<br />
5 CTLPIO0_5 PIO0_5 <br />
0<br />
0 =<br />
1 =<br />
6 CTLPIO0_6 PIO0_6 <br />
0<br />
0 =<br />
1 =<br />
7 CTLPIO0_7 PIO0_7 <br />
0<br />
0 =<br />
1 =<br />
8 CTLPIO0_8 PIO0_8 <br />
0<br />
0 =<br />
1 =<br />
9 CTLPIO0_9 PIO0_9 <br />
0<br />
0 =<br />
1 =<br />
10 CTLPIO0_10 PIO0_10 <br />
0<br />
0 =<br />
1 =<br />
11 CTLPIO0_11 PIO0_11 <br />
0<br />
0 =<br />
1 =<br />
31:12 - - 0<br />
5.6.4.2 <br />
DSWAKEEN<br />
Table 5-54: (DSWAKEEN,<br />
0x4004 8204) <br />
0 ERPIO0_0 PIO0_0 <br />
0<br />
0 = <br />
1 = <br />
1 ERPIO0_1 PIO0_1 <br />
0<br />
0 = <br />
1 = <br />
2 ERPIO0_2 PIO0_2 <br />
0<br />
0 = <br />
1 = <br />
56 www.xinnovatech.com
XN62Lxxx<br />
3 ERPIO0_3 PIO0_3 <br />
0<br />
0 = <br />
1 = <br />
4 ERPIO0_4 PIO0_4 <br />
0<br />
0 = <br />
1 = <br />
5 ERPIO0_5 PIO0_5 <br />
0<br />
0 = <br />
1 = <br />
6 ERPIO0_6 PIO0_6 <br />
0<br />
0 = <br />
1 = <br />
7 ERPIO0_7 PIO0_7 <br />
0<br />
0 = <br />
1 = <br />
8 ERPIO0_8 PIO0_8 <br />
0<br />
0 = <br />
1 = <br />
9 ERPIO0_9 PIO0_9 <br />
0<br />
0 = <br />
1 = <br />
10 ERPIO0_10 PIO0_10 <br />
0<br />
0 = <br />
1 = <br />
11 ERPIO0_11 PIO0_11 <br />
0<br />
0 = <br />
1 = <br />
31:12 <br />
5.6.4.3 <br />
DSWAKECLR <br />
1 <br />
<br />
<br />
Table 5-55: (DSWAKECLR,<br />
0x4004 8208) <br />
0 RSRPIO0_0 PIO0_0 <br />
0<br />
0 = .<br />
1 = 1 <br />
www.xinnovatech.com 57
XN62Lxxx<br />
1 RSRPIO0_1 PIO0_1 <br />
0<br />
0 = .<br />
1 = 1 <br />
2 RSRPIO0_2 PIO0_2 <br />
0<br />
0 = .<br />
1 = 1 <br />
3 RSRPIO0_3 PIO0_3 <br />
0<br />
0 = .<br />
1 = 1 <br />
4 RSRPIO0_4 PIO0_4 <br />
0<br />
0 = .<br />
1 = 1 <br />
5 RSRPIO0_5 PIO0_5 <br />
0<br />
0 = .<br />
1 = 1 <br />
6 RSRPIO0_6 PIO0_6 <br />
0<br />
0 = .<br />
1 = 1 <br />
7 RSRPIO0_7 PIO0_7 <br />
0<br />
0 = .<br />
1 = 1 <br />
8 RSRPIO0_8 PIO0_8 <br />
0<br />
0 = .<br />
1 = 1 <br />
9 RSRPIO0_9 PIO0_9 <br />
0<br />
0 = .<br />
1 = 1 <br />
10 RSRPIO0_10 PIO0_10 <br />
0<br />
0 = .<br />
1 = 1 <br />
11 RSRPIO0_11 PIO0_11 <br />
0<br />
0 = .<br />
1 = 1 <br />
31:12 - -<br />
5.6.4.4 <br />
<br />
Table 5-56: (DSWAKE,<br />
0x4004 820C) <br />
58 www.xinnovatech.com
XN62Lxxx<br />
0 SRPIO0_0 PIO0_0 <br />
0<br />
0 =<br />
1 = <br />
1 SRPIO0_1 PIO0_1 <br />
0<br />
0 =<br />
1 = <br />
2 SRPIO0_2 PIO0_2 <br />
0<br />
0 =<br />
1 = <br />
3 SRPIO0_3 PIO0_3 <br />
0<br />
0 =<br />
1 = <br />
4 SRPIO0_4 PIO0_4 <br />
0<br />
0 =<br />
1 = <br />
5 SRPIO0_5 PIO0_5 <br />
0<br />
0 =<br />
1 = <br />
6 SRPIO0_6 PIO0_6 <br />
0<br />
0 =<br />
1 = <br />
7 SRPIO0_7 PIO0_7 <br />
0<br />
0 =<br />
1 = <br />
8 SRPIO0_8 PIO0_8 <br />
0<br />
0 =<br />
1 = <br />
9 SRPIO0_9 PIO0_9 <br />
0<br />
0 =<br />
1 = <br />
10 SRPIO0_10 PIO0_10 <br />
0<br />
0 =<br />
1 = <br />
11 SRPIO0_11 PIO0_11 <br />
0<br />
0 =<br />
1 = <br />
31:12 - -<br />
www.xinnovatech.com 59
XN62Lxxx<br />
5.6.5 <br />
5.6.5.1 <br />
<br />
0<br />
<br />
1<br />
Table 5-57: (PRESETCTRL,<br />
0x4004 8004) <br />
<br />
0 SPI_RST_N SPI 1<br />
0 SPI <br />
1 SPI <br />
1 TWS_RST_N TWS 1<br />
0 TWS <br />
1 TWS <br />
2 UART0_RST_N UART0 1<br />
0 UART0 <br />
1 UART0 <br />
3 UART1_RST_N UART1 1<br />
0 UART1 <br />
1 UART1 <br />
4 CT16B0_RST_N 16 / 0 (CT16B0) 1<br />
0 CT16B0 <br />
1 CT16B0 <br />
5 CT16B1_RST_N 16 / 1 (CT16B1) 1<br />
0 CT16B1 <br />
1 CT16B1 <br />
6 CT32B0_RST_N 32 / 0 (CT32B0) 1<br />
0 CT32B0 <br />
1 CT32B0 <br />
7 CT32B1_RST_N 32 / 1 (CT32B1) 1<br />
0 CT32B1 <br />
1 CT32B1 <br />
8 CMP_RST_N 1<br />
0 <br />
1 <br />
<br />
9 XDSP_RST_N xDSP 1<br />
0 xDSP <br />
1 xDSP <br />
10 DMA_RST_N DMA 1<br />
0 DMA <br />
60 www.xinnovatech.com
XN62Lxxx<br />
1 DMA <br />
11 PWM0_RST_N PWM0 1<br />
0 PWM0 <br />
1 PWM0 <br />
12 PWM1_RST_N PWM1 1<br />
0 PWM1 <br />
1 PWM1 <br />
13 PWM2_RST_N PWM2 1<br />
0 PWM2 <br />
1 PWM2 <br />
14 ADC0_RST_N ADC0 1<br />
0 ADC0 <br />
1 ADC0 <br />
15 ADC1_RST_N ADC1 1<br />
0 ADC1 <br />
1 ADC1 <br />
16 ADC2_RST_N ADC2 1<br />
0 ADC2 <br />
1 ADC2 <br />
17 DAC_RST_N DAC 1<br />
0 DAC <br />
1 DAC <br />
18 UART2_RST_N UART2 1<br />
0 UART2 <br />
1 UART2 <br />
19 UART3_RST_N UART3 1<br />
0 UART3 <br />
1 UART3 <br />
31:20 - - 0x0<br />
5.7 I/O<br />
<br />
XN62L <br />
IOCON <br />
I/O <br />
• <br />
• /<br />
• <br />
• ADC <br />
www.xinnovatech.com 61
XN62Lxxx<br />
• IO <br />
5.7.1 IOCON<br />
PIO0_10<br />
PIO0_11 Table 5-58: IOCON ( TWS )<br />
<br />
2:0 FUNC 000<br />
000 0 ( ).<br />
001 1.<br />
010 2.<br />
011 3.<br />
100 4.<br />
101 5.<br />
110 6.<br />
111 .<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 <br />
1 <br />
5 - . 0<br />
6 INV 0<br />
0 <br />
1 <br />
7 ADMODE / 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV 0<br />
0 <br />
1 <br />
10 OD 0<br />
0 <br />
1 <br />
<br />
V DD (IO).<br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
62 www.xinnovatech.com
XN62Lxxx<br />
0x3<br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
<br />
31:16 - - . 0<br />
5.7.1.1 <br />
IOCON FUNC GPIO (FUNC = 000) <br />
GPIO DIR <br />
<br />
GPIOnDIR .<br />
5.7.1.2 <br />
IOCON MODE <br />
TWS PIO0_10 PIO0_11<br />
<br />
5.7.1.3 <br />
<br />
PIO0_27PIO0_28<br />
PIO0_29PIO0_12<br />
5.7.1.4 <br />
PIO0_10 PIO0_11 I/O <br />
V DD(IO) .<br />
5.7.1.5 A/D <br />
A/D <br />
ADC A/D <br />
5.7.1.6 TWS (I 2 C )<br />
TWS PIO0_10 PIO0_11 <br />
TWS <br />
PIO0_10 PIO0_11 (20 mA)<br />
5.7.1.7 <br />
G PIO <br />
www.xinnovatech.com 63
XN62Lxxx<br />
S_MODE 2 37<br />
= 1 PCLK0 6 <br />
IOCONFIGCLKDIV0 6 <br />
<br />
t pulse <br />
t pulse < t PCLKn × S_MODE<br />
<br />
t pulse < t PCLKn × (S_MODE + 1)<br />
(S_MODE<br />
<br />
SPI <br />
(S_MODE)<br />
5.7.2 IOCON<br />
Table 5-59: I/O <br />
( 0x4004 4000)<br />
<br />
<br />
- R/W 0x000 . -<br />
- R/W 0x004 . -<br />
PIO0_19 R/W 0x008 PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1 0x0000 0090<br />
PIO0_20 R/W 0x00C PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2 0x0000 0090<br />
PIO0_21 R/W 0x010 PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0 0x0000 0090<br />
PIO0_22 R/W 0x014 PIO0_22/ACMP0_I3/PWM1_1 0x0000 0090<br />
PIO0_23 R/W 0x018 PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0/PWM_FAULT2 0x0000 0090<br />
PIO0_24 R/W 0x01C PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1/PWM_FAULT3 0x0000 0090<br />
PIO0_25 R/W 0x020 SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25 0x0000 0090<br />
PIO0_26 R/W 0x024 SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26 0x0000 0090<br />
PIO0_27 R/W 0x028 PIO0_27/ACMP0_O/DA0/PWM_FAULT0 0x0000 0090<br />
PIO2_12 R/W 0x02C PIO2_12/RXD1/ PWM2_0 0x0000 0090<br />
PIO2_13 R/W 0x030 PIO2_13/TXD1/ PWM2_1 0x0000 0090<br />
PIO2_14 R/W 0x034 PIO2_14/ PWM2_2/TXD3. 0x0000 0090<br />
PIO2_15 R/W 0x038 PIO2_15/ PWM2_3/RXD3. 0x0000 0090<br />
PIO0_28 R/W 0x03C PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0 0x0000 0090<br />
PIO0_29 R/W 0x040 PIO0_29/ROSC/CT16B0_CAP1/CT16B0_MAT1/ PWM1_6 0x0000 0090<br />
PIO0_0 R/W 0x044 PIO0_0/PWM0_0 0x0000 0090<br />
PIO0_1 R/W 0x048 PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0 0x0000 0090<br />
PIO0_2 R/W 0x04C PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1 0x0000 0090<br />
- R/W 0x050 -<br />
PIO0_3 R/W 0x054 PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_1/PWM1_4 0x0000 0090<br />
PIO0_4 R/W 0x058 PIO0_4/CT32B0_CAP3/CT32B0_MAT3/PWM0_2/PWM1_5 0x0000 0090<br />
PIO0_5 R/W 0x05C PIO0_5/ PWM0_3. 0x0000 0090<br />
PIO0_6 R/W 0x060 PIO0_6/CT32B1_CAP0/CT32B1_MAT0/PWM0_4/PWM1_2 0x0000 0090<br />
64 www.xinnovatech.com
XN62Lxxx<br />
PIO0_7 R/W 0x064 PIO0_7/CT32B1_CAP1/CT32B1_MAT1/PWM0_5/PWM1_3 0x0000 0090<br />
PIO0_8 R/W 0x068 PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_6 0x0000 0090<br />
PIO0_9 R/W 0x06C PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_7 0x0000 0090<br />
PIO2_0 R/W 0x070 PIO2_0/CT16B0_CAP0/CT16B0_MAT0/PWM1_0 0x0000 0090<br />
PIO2_1 R/W 0x074 <br />
0x0000 0090<br />
PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0/PWM_FAULT2/PWM1_1<br />
PIO2_2 R/W 0x078 <br />
0x0000 0090<br />
PIO2_2/CT16B1_CAP0/CT16B1_MAT0/TXD0/PWM_FAULT3/PWM1_2<br />
PIO2_3 R/W 0x07C PIO2_3/CT16B1_CAP1/CT16B1_MAT1/PWM1_3 0x0000 0090<br />
PIO2_4 R/W 0x080 PIO2_4/CT32B0_CAP0/CT32B0_MAT0/PWM1_4 0x0000 0090<br />
PIO2_5 R/W 0x084 PIO2_5/CT32B0_CAP1/CT32B0_MAT1/ PWM1_5 0x0000 0090<br />
PIO2_6 R/W 0x088 PIO2_6/CT32B0_CAP2/CT32B0_MAT2/PWM2_4/TXD2 0x0000 0090<br />
PIO2_7 R/W 0x08C PIO2_7/CT32B0_CAP3/CT32B0_MAT3/PWM2_5/RXD2 0x0000 0090<br />
PIO0_10 R/W 0x090 PIO0_10/SCL 0x0000 0080<br />
PIO0_11 R/W 0x094 PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0 0x0000 0080<br />
PIO0_12 R/W 0x098 PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1// PWM1_6 0x0000 0090<br />
PIO0_13 R/W 0x09C RESET/PIO0_13. 0x0000 0090<br />
PIO0_14 R/W 0x0A0 PIO0_14/SPI_CLK/TXD2. 0x0000 0090<br />
PIO0_15 R/W 0x0A4 PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/RXD2 0x0000 0090<br />
PIO0_16 R/W 0x0A8 PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/TXD3 0x0000 0090<br />
PIO0_17 R/W 0x0AC PIO0_17/SPI_MOSI/RXD3. 0x0000 0090<br />
PIO0_18 R/W 0x0B0 PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0 0x0000 0090<br />
PIO0_30 R/W 0x0B4 R/PIO0_30/AD0. 0x0000 0090<br />
PIO0_31 R/W 0x0B8 R/PIO0_31/AD1/PWM1_7 0x0000 0090<br />
PIO1_0 R/W 0x0BC R/PIO1_0/AD2. 0x0000 0090<br />
PIO1_1 R/W 0x0C0 R/PIO1_1/AD3/ PWM0_4/PWM1_4. 0x0000 0090<br />
PIO1_2 R/W 0x0C4 PIO1_2/SWDIO/AD4. 0x0000 0090<br />
PIO1_3 R/W 0x0C8 PIO1_3/AD5/WAKEUP. 0x0000 0090<br />
PIO1_4 R/W 0x0CC PIO1_4/AD6/ PWM0_5/PWM1_5. 0x0000 0090<br />
PIO1_5 R/W 0x0D0 PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0 0x0000 0090<br />
PIO1_6 R/W 0x0D4 PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1 0x0000 0090<br />
- - 0x0D8 . -<br />
- - 0x0DC . -<br />
PIO2_8 R/W 0x0E0 PIO2_8/CT32B1_CAP0/CT32B1_MAT0/PWM2_6/AD8 0x0000 0090<br />
PIO2_9 R/W 0x0E4 PIO2_9/CT32B1_CAP1/CT32B1_MAT1/PWM2_7/AD9 0x0000 0090<br />
PIO2_10 R/W 0x0E8 PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1/AD10 0x0000 0090<br />
PIO2_11 R/W 0x0EC PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1/AD11 0x0000 0090<br />
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5.7.2.1 PIO0_0 IOCON <br />
Table 5-60: PIO0_0 (PIO0_0, 0x4004 4044) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
PIO0_0.<br />
0x1~2 <br />
0x3<br />
0x4<br />
PWM0_0.<br />
QSPI_CS.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
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5.7.2.2 PIO0_1 IOCON <br />
Table 5-61: PIO0_1 (PIO0_1, 0x4004 4048) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_1.<br />
.<br />
RXD0.<br />
CT32B0_CAP0.<br />
CT32B0_MAT0.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
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5.7.2.3 PIO0_2 IOCON <br />
Table 5-62: PIO0_2 (PIO0_2, 0x4004 404C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_2.<br />
.<br />
TXD0.<br />
CT32B0_CAP1.<br />
CT32B0_MAT1.<br />
3 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
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XN62Lxxx<br />
5.7.2.4 PIO0_3 IOCON <br />
Table 5-63: PIO0_3 (PIO0_3, 0x4004 4054) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO0_3.<br />
QSPI_CLK.<br />
.<br />
CT32B0_CAP2.<br />
CT32B0_MAT2.<br />
PWM0_1<br />
PWM1_4<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
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31:16 - - . 0<br />
5.7.2.5 PIO0_4 IOCON <br />
Table 5-64: PIO0_4 (PIO0_4, 0x4004 4058) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO0_4.<br />
QSPI_WP.<br />
.<br />
CT32B0_CAP3.<br />
CT32B0_MAT3.<br />
PWM0_2<br />
PWM1_5<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
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XN62Lxxx<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.6 PIO0_5 IOCON <br />
Table 5-65: PIO0_5 (PIO0_5, 0x4004 405C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
PIO0_5.<br />
QSPI_HOLD<br />
<br />
PWM0_3.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
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0x6<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.7 PIO0_6 IOCON <br />
Table 5-66: PIO0_6 (PIO0_6, 0x4004 4060) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO0_6.<br />
QSPI_DI<br />
.<br />
CT32B1_CAP0.<br />
CT32B1_MAT0.<br />
PWM0_4.<br />
PWM1_2.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
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XN62Lxxx<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.8 PIO0_7 IOCON <br />
Table 5-67: PIO0_7 (PIO0_7, 0x4004 4064) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO0_7.<br />
QSPI_DO<br />
.<br />
CT32B1_CAP1.<br />
CT32B1_MAT1.<br />
PWM0_5.<br />
PWM1_3.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
www.xinnovatech.com 73
XN62Lxxx<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.9 PIO0_8 IOCON <br />
Table 5-68: PIO0_8 (PIO0_8, 0x4004 4068) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_8.<br />
.<br />
RXD1.<br />
CT32B1_CAP2.<br />
CT32B1_MAT2.<br />
PWM0_6.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
IOCONFIGCLKDIV0.<br />
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XN62Lxxx<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.10 PIO0_9 IOCON <br />
Table 5-69: PIO0_9 (PIO0_9, 0x4004 406C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_9.<br />
.<br />
TXD1.<br />
CT32B1_CAP3.<br />
CT32B1_MAT3.<br />
PWM0_7.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
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XN62Lxxx<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.1 PIO0_10 IOCON <br />
Table 5-70: PIO0_10 (PIO0_10, 0x4004 4090) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO0_10.<br />
.<br />
TWS SCL <br />
5:3 - . 000<br />
6 INV 0<br />
0 .<br />
1 .<br />
10:7 - - . 0001<br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x0<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
.<br />
31:16 - . 0<br />
5.7.2.2 PIO0_11 IOCON <br />
Table 5-71: PIO0_11 (PIO0_11, 0x4004 4094) <br />
<br />
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XN62Lxxx<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_11.<br />
.<br />
TWS SDA .<br />
CT16B0_CAP0.<br />
CT16B0_MAT0.<br />
5:3 - - . 000<br />
6 INV 0<br />
0 .<br />
1 .<br />
10:7 - - . 0001<br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x0<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
.<br />
31:16 - . 0<br />
5.7.2.3 PIO0_12 IOCON <br />
Table 5-72: PIO0_12 (PIO0_12, 0x4004 4098) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO0_12.<br />
.<br />
CLKOUT.<br />
CT16B0_CAP1.<br />
CT16B0_MAT1.<br />
.<br />
PWM1_6.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
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XN62Lxxx<br />
0 .<br />
1 .<br />
5 . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.4 PIO0_13 IOCON <br />
Table 5-73: RESET_PIO0_13 (RESET_PIO0_13, 0x4004 409C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
RESET.<br />
PIO0_13.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 . 0<br />
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6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.5 PIO0_14 IOCON <br />
Table 5-74: PIO0_14 (PIO0_14, 0x4004 40A0) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_14.<br />
.<br />
SCK.<br />
CLKOUT.<br />
.<br />
TXD2.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
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5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.6 PIO0_15 IOCON <br />
Table 5-75: PIO0_15 (PIO0_15, 0x4004 40A4) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_15.<br />
.<br />
SSEL.<br />
CT16B1_CAP0.<br />
CT16B1_MAT0.<br />
RXD2.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
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1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.7 PIO0_16 IOCON <br />
Table 5-76: PIO0_16 (PIO0_16, 0x4004 40A8) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_16.<br />
.<br />
MISO.<br />
CT16B1_CAP1.<br />
CT16B1_MAT1.<br />
TXD3.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
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0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.8 PIO0_17 IOCON <br />
Table 5-77: PIO0_17 (PIO0_17, 0x4004 40AC) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO0_17.<br />
.<br />
MOSI.<br />
0x3~4 .<br />
0x5<br />
RXD3.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
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0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.9 PIO0_18 IOCON <br />
Table 5-78: PIO0_18 (PIO0_18, 0x4004 40B0) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_18.<br />
.<br />
SWCLK.<br />
CT32B0_CAP0.<br />
CT32B0_MAT0.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
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0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.10 PIO0_19 IOCON <br />
Table 5-79: PIO0_19 (PIO0_19, 0x4004 4008) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_19.<br />
.<br />
ACMP0_I0.<br />
CT32B0_CAP1.<br />
CT32B0_MAT1.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
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0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.11 PIO0_20 IOCON <br />
Table 5-80: PIO0_20 (PIO0_20, 0x4004 400C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_20.<br />
.<br />
ACMP0_I1.<br />
CT32B0_CAP2.<br />
CT32B0_MAT2.<br />
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3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.12 PIO0_21 IOCON <br />
Table 5-81: PIO0_21 (PIO0_21, 0x4004 4010) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO0_21.<br />
.<br />
ACMP0_I2.<br />
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0x3<br />
0x4<br />
0x5<br />
CT32B0_CAP3.<br />
CT32B0_MAT3.<br />
PWM1_0<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.13 PIO0_22 IOCON <br />
Table 5-82: PIO0_22 (PIO0_22, 0x4004 4014) <br />
<br />
2:0 FUNC . 000<br />
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0x0<br />
0x1<br />
0x2<br />
PIO0_22.<br />
.<br />
ACMP0_I3.<br />
0x3~4 .<br />
0x5<br />
PWM1_1<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.14 PIO0_23 IOCON <br />
Table 5-83: PIO0_23 (PIO0_23, 0x4004 4018) <br />
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<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_23.<br />
.<br />
ACMP1_I0.<br />
CT32B1_CAP0.<br />
CT32B1_MAT0.<br />
PWM_FAULT2<br />
3 - - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
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5.7.2.15 PIO0_24 IOCON <br />
Table 5-84: PIO0_24 (PIO0_24, 0x4004 401C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_24.<br />
.<br />
ACMP1_I1.<br />
CT32B1_CAP1.<br />
CT32B1_MAT1.<br />
PWM_FAULT3<br />
3 - - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
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0x6<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.16 PIO0_25 IOCON <br />
Table 5-85: SWDIO_PIO0_25 (SWDIO_PIO0_25, 0x4004 4020) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
SWDIO.<br />
.<br />
ACMP1_I2.<br />
CT32B1_CAP2.<br />
CT32B1_MAT2.<br />
.<br />
PIO0_25.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
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0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.17 PIO0_26 IOCON <br />
Table 5-86: SWCLK_PIO0_26 (SWCLK_PIO0_26, 0x4004 4024) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
SWCLK.<br />
.<br />
ACMP1_I3.<br />
CT32B1_CAP3.<br />
CT32B1_MAT3.<br />
.<br />
PIO0_26.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
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0x3<br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.18 PIO0_27 IOCON <br />
Table 5-87: PIO0_27 (PIO0_27, 0x4004 4028) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO0_27.<br />
.<br />
ACMP0_O.<br />
0x3~4 .<br />
0x5<br />
0x6<br />
PWM_FAULT0<br />
DA0<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
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0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.19 PIO0_28 IOCON <br />
Table 5-88: PIO0_28 (PIO0_28, 0x4004 403C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO0_28.<br />
.<br />
ACMP1_O.<br />
CT16B0_CAP0.<br />
CT16B0_MAT0.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
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0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.20 PIO0_29 IOCON <br />
Table 5-89: PIO0_29 (PIO0_29, 0x4004 4040) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO0_29.<br />
.<br />
.<br />
CT16B0_CAP1.<br />
CT16B0_MAT1.<br />
PWM1_6.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
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12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - 0<br />
5.7.2.1 PIO0_30 IOCON <br />
Table 5-90: PIO0_30 (PIO0_30, 0x4004 40B4) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
.<br />
PIO0_30.<br />
.<br />
AD0.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
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1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.2 PIO0_31 IOCON <br />
Table 5-91: PIO0_31 (PIO0_31, 0x4004 40B8) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
.<br />
PIO0_31.<br />
.<br />
AD1.<br />
.<br />
PWM1_7.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
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1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.3 PIO1_0 IOCON <br />
Table 5-92: PIO1_0 (PIO1_0, 0x4004 40BC) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
.<br />
PIO1_0.<br />
AD2.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
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1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.4 PIO1_1 IOCON <br />
Table 5-93: PIO1_1 (PIO1_1, 0x4004 40C0) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
.<br />
PIO1_0.<br />
AD3.<br />
0x3~4 .<br />
0x5<br />
0x6<br />
PWM0_4.<br />
PWM1_4.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
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8 - . 0<br />
9 DRV . 0<br />
0 2mA .<br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.5 PIO1_2 IOCON <br />
Table 5-94: PIO1_2 (PIO1_2, 0x4004 40C4) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO1_2.<br />
SWDIO.<br />
AD4.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
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8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.6 PIO1_3 IOCON <br />
Table 5-95: PIO1_3 (PIO1_3, 0x4004 40C8) <br />
<br />
2:0 FUNC . <br />
WAKEUP <br />
000<br />
0x0<br />
0x1<br />
PIO1_3.<br />
AD5.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
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9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.7 PIO1_4 IOCON <br />
Table 5-96: PIO1_4 (PIO1_4, 0x4004 40CC) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
PIO1_4.<br />
AD6.<br />
0x2~4 .<br />
0x5<br />
0x6<br />
PWM0_5.<br />
PWM1_5.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
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1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - -. 0<br />
5.7.2.8 PIO1_5 IOCON <br />
Table 5-97: PIO1_5 (PIO1_5, 0x4004 40D0) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
PIO1_5.<br />
AD7.<br />
CT16B1_CAP0.<br />
CT16B1_MAT0.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
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0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.9 PIO1_6 IOCON <br />
Table 5-98: PIO1_6 (PIO1_6, 0x4004 40D4) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO1_6.<br />
CT16B1_CAP1.<br />
CT16B1_MAT1.<br />
0x3~4 .<br />
0x5<br />
PWM_FAULT1.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
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1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.10 PIO2_0 IOCON <br />
Table 5-99: PIO2_0 (PIO2_0, 0x4004 4070) <br />
Z` <br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
PIO2_0.<br />
CT16B0_CAP0.<br />
0x2~3 .<br />
0x4<br />
0x5<br />
0x6<br />
CT16B0_MAT0.<br />
.<br />
PWM1_0.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
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0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.11 PIO2_1 IOCON <br />
Table 5-100: PIO2_1 (PIO2_1, 0x4004 4074) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO2_1.<br />
CT16B0_CAP1.<br />
.<br />
CT16B0_MAT1.<br />
RXD0.<br />
PWM_FAULT2.<br />
PWM1_1.<br />
3 - - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
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5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - - . 1<br />
8 - - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.12 PIO2_2 IOCON <br />
Table 5-101: PIO2_2 (PIO2_2, 0x4004 4078) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
PIO2_2.<br />
.<br />
CT16B1_CAP0.<br />
CT16B1_MAT0.<br />
TXD0.<br />
PWM_FAULT3.<br />
PWM1_2.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
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XN62Lxxx<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.13 PIO2_3 IOCON <br />
Table 5-102: PIO2_3 (PIO2_3, 0x4004 407C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
PIO2_3.<br />
.<br />
CT16B1_CAP1.<br />
CT16B1_MAT1.<br />
0x4~5 .<br />
0x6<br />
PWM1_3.<br />
3 - 0<br />
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XN62Lxxx<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.14 PIO2_4 IOCON <br />
Table 5-103: PIO2_4 (PIO2_4, 0x4004 4080) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO2_4.<br />
.<br />
CT32B0_CAP0.<br />
CT32B0_MAT0.<br />
.<br />
PWM1_4.<br />
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XN62Lxxx<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.15 PIO2_5 IOCON <br />
Table 5-104: PIO2_5 (PIO2_5, 0x4004 4084) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
PIO2_5.<br />
.<br />
CT32B0_CAP1.<br />
CT32B0_MAT1.<br />
.<br />
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XN62Lxxx<br />
0x5<br />
PWM1_5.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.16 PIO2_6 IOCON <br />
Table 5-105: PIO2_6 (PIO2_6, 0x4004 4088) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
PIO2_6.<br />
.<br />
CT32B0_CAP2.<br />
CT32B0_MAT2.<br />
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XN62Lxxx<br />
0x4<br />
0x5<br />
0x6<br />
.<br />
PWM2_4.<br />
TXD2.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.17 PIO2_7 IOCON <br />
Table 5-106: PIO2_7 (PIO2_7, 0x4004 408C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
PIO2_7.<br />
.<br />
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XN62Lxxx<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
CT32B0_CAP3.<br />
CT32B0_MAT3.<br />
.<br />
PWM2_5.<br />
RXD2.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - . 1<br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
5.7.2.18 PIO2_8 IOCON <br />
Table 5-107: PIO2_8 (PIO2_8, 0x4004 40E0) <br />
<br />
2:0 FUNC . 000<br />
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XN62Lxxx<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO2_8.<br />
.<br />
CT32B1_CAP0.<br />
CT32B1_MAT0.<br />
AD8<br />
PWM2_6.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
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XN62Lxxx<br />
5.7.2.19 PIO2_9 IOCON <br />
Table 5-108: PIO2_9 (PIO2_9, 0x4004 40E4) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO2_9.<br />
.<br />
CT32B1_CAP1.<br />
CT32B1_MAT1.<br />
AD9<br />
PWM2_7.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
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XN62Lxxx<br />
0x6<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.20 PIO2_10 IOCON <br />
Table 5-109: PIO2_10 (PIO2_10, 0x4004 40E8) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO2_10.<br />
.<br />
CT32B1_CAP2.<br />
CT32B1_MAT2.<br />
AD10.<br />
TXD1.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE 1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
0x2<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
116 www.xinnovatech.com
XN62Lxxx<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.21 PIO2_11 IOCON <br />
Table 5-110: PIO2_11 (PIO2_11, 0x4004 40EC) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
PIO2_11.<br />
.<br />
CT32B1_CAP3.<br />
CT32B1_MAT3.<br />
AD11.<br />
RXD1.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 ADMODE <br />
1<br />
0 <br />
1 <br />
8 - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
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XN62Lxxx<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.1 PIO2_12 IOCON <br />
Table 5-111: PIO2_12 (PIO2_12, 0x4004 402C) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
PIO2_12.<br />
.<br />
PWM2_0.<br />
RXD1.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - - 1<br />
8 - - 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV <br />
000<br />
0x0<br />
IOCONFIGCLKDIV0.<br />
118 www.xinnovatech.com
XN62Lxxx<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV1.<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - -. 0<br />
5.7.2.2 PIO2_13 IOCON <br />
Table 5-112: PIO2_13 (PIO2_13, 0x4004 4030) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
PIO2_13.<br />
.<br />
PWM2_1.<br />
TXD1.<br />
3 - - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 - - . 1<br />
8 - - . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
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XN62Lxxx<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.3 PIO2_14 IOCON <br />
Table 5-113: PIO2_14 (PIO2_14, 0x4004 4034) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO2_14.<br />
<br />
PWM2_2.<br />
0x3~4 <br />
0x5<br />
TXD3.<br />
3 - 0<br />
4 MODE <br />
()<br />
. 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 . 1<br />
8 . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
120 www.xinnovatech.com
XN62Lxxx<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - - . 0<br />
5.7.2.4 PIO2_15 IOCON <br />
Table 5-114: PIO2_15 (PIO2_15, 0x4004 4038) <br />
<br />
2:0 FUNC . 000<br />
0x0<br />
0x1<br />
0x2<br />
PIO2_15.<br />
.<br />
PWM2_3.<br />
0x3~5 .<br />
0x6<br />
RXD3.<br />
3 - 0<br />
4 MODE <br />
(). 1<br />
0 .<br />
1 .<br />
5 - . 0<br />
6 INV 0<br />
0 .<br />
1 .<br />
7 . 1<br />
8 . 0<br />
9 DRV . 0<br />
0 <br />
1 <br />
.<br />
10 OD 0<br />
0 <br />
1 <br />
12:11 S_MODE 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
<br />
1 <br />
1 <br />
2 <br />
2 <br />
3 <br />
3 <br />
15:13 CLK_DIV 000<br />
0x0<br />
0x1<br />
IOCONFIGCLKDIV0.<br />
IOCONFIGCLKDIV1.<br />
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XN62Lxxx<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
IOCONFIGCLKDIV2.<br />
IOCONFIGCLKDIV3.<br />
IOCONFIGCLKDIV4.<br />
IOCONFIGCLKDIV5.<br />
IOCONFIGCLKDIV6.<br />
31:16 - . 0<br />
122 www.xinnovatech.com
XN62Lxxx<br />
6 PWM<br />
6.1 <br />
XN62L 3 <br />
PWM0PWM1PWM2<br />
<br />
4 8<br />
<br />
PWM 2 <br />
4 <br />
0~100%<br />
<br />
PWM 32 <br />
2 PWM PWM_PCLK()<br />
PWM <br />
PWM <br />
PWM PWM <br />
ADC GPIO <br />
PWM <br />
PWM <br />
8 <br />
PWM <br />
A/D <br />
6.1.1 <br />
• 3 <br />
• System Clock<br />
• 24 PWM <br />
– <br />
– <br />
– <br />
• <br />
– /<br />
– <br />
– <br />
PWM – <br />
• PWM <br />
• 32 <br />
• <br />
• 1 16 <br />
• <br />
PWM • 8 <br />
• <br />
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XN62Lxxx<br />
• PWM <br />
• PWM <br />
– PWM <br />
– GPIO <br />
– <br />
– ADC <br />
6.1.2 <br />
Figure 6-1 PWMn (n=0,1,2)<br />
PCLK<br />
Edge or Center<br />
Align<br />
Control<br />
PWM Counter<br />
Modulus<br />
Prescaler<br />
PWM Counter<br />
PWM Control<br />
Sources<br />
-ADC<br />
-GPIO<br />
-Timer<br />
PWM Value<br />
Register 0<br />
Compare Unit 0<br />
PWM 0<br />
PWM Value<br />
Register 1<br />
Compare Unit 1<br />
PWM 1<br />
PWM Value<br />
Register 2<br />
PWM Value<br />
Register 3<br />
PWM Value<br />
Register 4<br />
PWM Value<br />
Register 5<br />
Compare Unit 2<br />
Compare Unit 3<br />
Compare Unit 4<br />
Compare Unit 5<br />
MUX/SWAP<br />
/DEADTIME<br />
Insertion and<br />
Output Control<br />
PWM Fault Protection<br />
Polarity Control<br />
PWM Channel Mask<br />
PWM 2<br />
PWM 3<br />
PWM 4<br />
PWM 5<br />
PWM Value<br />
Register 6<br />
Compare Unit 6<br />
PWM 6<br />
PWM Value<br />
Register 7<br />
Compare Unit 7<br />
PWM 7<br />
PWM Compare<br />
Output<br />
Polarity Control<br />
Software Control<br />
and Output Mode<br />
Setting<br />
Fliters Fault Input [3:0]<br />
Figure 6-1: PWMn(n=0,1,2) <br />
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XN62Lxxx<br />
6.2 <br />
PWM <br />
Table 6-1: PWM <br />
<br />
PWM0_0 ~ PWM0_7 PWM0 <br />
PWM1_0 ~ PWM1_7 PWM1 <br />
PWM2_0 ~ PWM2_7 PWM2 <br />
PWM_FAULT0 ~ PWM_FAULT3 <br />
PWM 6.3 <br />
<br />
Table 6-2: PWM <br />
( 0x4005 8000 PWM0/0x4005 C000 PWM1/0x4006 0000 PWM2)<br />
<br />
CTRL R/W 0x000 0x0<br />
FCTRL R/W 0x004 0x0<br />
FLTACK R/W 0x008 0x0<br />
OUTCTRL R/W 0x00C <br />
0x0<br />
CNTR RO 0x010 0x0<br />
CMOD R/W 0x014 0x0<br />
VAL0 R/W 0x018 0 0x0<br />
VAL1 R/W 0x01C 1 0x0<br />
VAL2 R/W 0x020 2 0x0<br />
VAL3 R/W 0x024 3 0x0<br />
VAL4 R/W 0x028 4 0x0<br />
VAL5 R/W 0x02C 5 0x0<br />
VAL6 R/W 0x030 6 0x0<br />
VAL7 R/W 0x034 7 0x0<br />
DTIM0 R/W 0x038 0 0xFFF<br />
DTIM1 R/W 0x03C 1 0xFFF<br />
DMAP1 R/W 0x040 <br />
1 0x0<br />
DMAP2 R/W 0x044 <br />
2 0x0<br />
CNFG R/W 0x048 0x0<br />
CCTRL R/W 0x04C 0x0<br />
PORT R/W 0x050 <br />
0x0<br />
ICCTRL R/W 0x054 <br />
. 0x0<br />
SCTRL R/W 0x058 0x0<br />
TMRSEL R/W 0x05C PWM 0x0<br />
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XN62Lxxx<br />
PCR R/W 0x060 0x0<br />
CNTRINI WO 0x064 0x0<br />
DELAYST R/W 0x068 PWMnPWM(n+1)<br />
0x0<br />
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XN62Lxxx<br />
6.3.1 PWM<br />
Table 6-3 PWM (CTRL) <br />
<br />
0 PWMEN PWM 0<br />
0 PWM <br />
PWM <br />
OUTCTLm =1<br />
1 PWM <br />
1 LDOK <br />
CTRL <br />
PRSC CMOD <br />
VALm 0<br />
PWM <br />
CTRL <br />
CMOD <br />
VALm PWM <br />
LDOK <br />
1<br />
PWM<br />
LDOK <br />
0<br />
0 0 <br />
1 CTRL <br />
CMOD <br />
VALm PWM <br />
2 PWMF <br />
1 PWMF 0 0<br />
0 <br />
0 : PWMF <br />
PWMF <br />
0 PWMF <br />
1 PWMF <br />
3 PWMRIE PWMF 0<br />
0 PWMF <br />
1 PWMF <br />
4 - - 0<br />
6:5 PRSC - PWM <br />
00<br />
: PRSC <br />
LDOK 1 PWM <br />
00 PWM <br />
01 PWM /2<br />
10 PWM /4<br />
11 PWM /8<br />
7 IPOL0 PWMn_0 PWMn_1 <br />
PWM 0<br />
0 PWM <br />
VAL0 <br />
1 PWM <br />
VAL1 <br />
8 IPOL1 PWMn_2 PWMn_3 <br />
PWM 0<br />
0 PWM <br />
VAL2 <br />
1 PWM <br />
VAL3 <br />
9 IPOL2 PWMn_4 PWMn_5 <br />
PWM 0<br />
0 PWM <br />
VAL4 <br />
1 PWM <br />
VAL5 <br />
10 IPOL3 PWMn_6 PWMn_7 <br />
PWM 0<br />
0 PWM <br />
VAL6 <br />
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1 PWM <br />
VAL7 <br />
11 HALF <br />
0<br />
0 <br />
1 <br />
15:12 LDFQ - PWM <br />
LDFQ /<br />
PWM <br />
HALF 0000<br />
: LDOK LDFQ<br />
<br />
LDFQ <br />
0000 PWM <br />
0001 2 PWM <br />
0010 3 PWM <br />
0011 4 PWM <br />
0100 5 PWM <br />
0101 6 PWM <br />
0110 7 PWM <br />
0111 8 PWM <br />
1000 9 PWM <br />
1001 10 PWM <br />
1010 11 PWM <br />
1011 12 PWM <br />
1100 13 PWM <br />
1101 14 PWM <br />
1110 15 PWM <br />
1111 16 PWM <br />
16 SOFTFAULT 0<br />
0 <br />
1 <br />
17 INIDIR 0<br />
0 PWM <br />
1 PWM <br />
18 LDOUTEN <br />
24 31 0<br />
23~19 - - <br />
timerADC <br />
0 <br />
1 <br />
24 CH0OUTEN 0 <br />
0<br />
0 <br />
1 <br />
25 CH1OUTEN 1 <br />
0<br />
0 <br />
1 <br />
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XN62Lxxx<br />
26 CH2OUTEN 2 <br />
0<br />
0 <br />
1 <br />
27 CH3OUTEN 3 <br />
0<br />
0 <br />
1 <br />
28 CH4OUTEN 4 <br />
0<br />
0 <br />
1 <br />
29 CH5OUTEN 5 <br />
0<br />
0 <br />
1 <br />
30 CH6OUTEN 6 <br />
0<br />
0 <br />
1 <br />
31 CH7OUTEN 7 <br />
0<br />
0 <br />
1 <br />
6.3.2 PWM<br />
Table 6-4 PWM (FCTRL)<br />
<br />
0 FMODE0 / PWM_FAULT0 . 0<br />
0 <br />
1 <br />
1 FIE0 PWM_FAULT0 0<br />
0 <br />
1 <br />
2 FMODE1 / PWM_FAULT1 . 0<br />
0 <br />
1 <br />
3 FIE1 PWM_FAULT1 0<br />
0 <br />
1 <br />
4 FMODE2 / PWM_FAULT2 . 0<br />
0 <br />
1 <br />
5 FIE2 PWM_FAULT2 0<br />
0 <br />
1 <br />
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6 FMODE3 / PWM_FAULT3 . 0<br />
0 <br />
1 <br />
7 FIE3 PWM_FAULT3 0<br />
0 <br />
1 <br />
8 FMODE4 /<br />
0COMPARATOR0<br />
. 0<br />
0 <br />
1 <br />
9 FIE4 0COMPARATOR0 0<br />
0 <br />
1 <br />
10 FMODE5 /<br />
1COMPARATOR1<br />
. 0<br />
0 <br />
1 <br />
11 FIE5 1COMPARATOR1 0<br />
0 <br />
1 <br />
12 FMODE6 /(CTRL<br />
SOFTFAULT) . 0<br />
0 <br />
1 <br />
13 FIE6 (CTRL SOFTFAULT) 0<br />
0 <br />
1 <br />
31:14 - - 0<br />
6.3.3 PWM<br />
Table 6-5 PWM (FLTACK) <br />
<br />
0 FTACK0 - 1 FFLAG00 <br />
0RE<br />
SET FTACK0 . 0<br />
PWM PWM <br />
PWM <br />
<br />
PWM 1 FTACK1 - 1 FFLAG10 <br />
0RESET<br />
FTACK1 .<br />
PWM PWM <br />
PWM <br />
<br />
PWM 2 FTACK2 - 1 FFLAG20 <br />
0 RESET FTACK2 . 0<br />
PWM PWM <br />
PWM <br />
<br />
PWM 3 FTACK3 - 1 FFLAG30 <br />
0RESET<br />
FTACK3 . 0<br />
PWM PWM <br />
PWM <br />
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XN62Lxxx<br />
<br />
PWM 4 FTACK4 1 FFLAG40 <br />
0RESET<br />
FTACK4 .<br />
PWM PWM <br />
PWM <br />
<br />
PWM 5 FTACK5 - 1 FFLAG50 <br />
0RESET<br />
FTACK5 . 0<br />
PWM PWM <br />
PWM <br />
<br />
PWM 6 FTACK6 - 1 FFLAG60 <br />
0RESET<br />
FTACK6 . 0<br />
PWM PWM <br />
PWM <br />
<br />
PWM 7 FTACK7 - 1 FFLAG70 <br />
0RESET<br />
FTACK7 . 0<br />
PWM PWM <br />
PWM <br />
<br />
PWM 15:8 - 0<br />
16 FFLAG0 <br />
PWM_FAULT0 <br />
2 PWM <br />
10<br />
FTACK0 1 FFLAG0 <br />
0 PWM_FAULT0 <br />
1 PWM_FAULT0 <br />
17 FPIN0 <br />
PWM_FAULT0 0<br />
0 0 PWM_FAULT0 <br />
1 1 PWM_FAULT0 <br />
18 FFLAG1 <br />
PWM_FAULT1 <br />
2 PWM <br />
10<br />
FTACK1 1 FFLAG1 <br />
0 PWM_FAULT1 <br />
1 PWM_FAULT1 <br />
19 FPIN1 <br />
PWM_FAULT1 0<br />
0 0 PWM_FAULT1 <br />
1 1 PWM_FAULT1 <br />
20 FFLAG2 <br />
PWM_FAULT2 <br />
2 PWM <br />
10<br />
FTACK2 1 FFLAG2 <br />
0 PWM_FAULT2 <br />
1 PWM_FAULT2 <br />
21 FPIN2 <br />
PWM_FAULT2 0<br />
0 0 PWM_FAULT2 <br />
1 1 PWM_FAULT2 <br />
22 FFLAG3 <br />
PWM_FAULT3 <br />
2 PWM <br />
10<br />
FTACK3 1 FFLAG3 <br />
0 PWM_FAULT3 <br />
1 PWM_FAULT3 <br />
23 FPIN3 <br />
PWM_FAULT3 0<br />
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0 0 PWM_FAULT3 <br />
1 1 PWM_FAULT3 <br />
24 FFLAG4 <br />
0COMPARATOR0<br />
2 PWM 0<br />
1FTACK4 1 FFLAG4 <br />
0 <br />
0COMPARATOR0<br />
1 <br />
0COMPARATOR0<br />
25 FPIN4 <br />
0COMPARATOR0 0<br />
0 0COMPARATOR0 0<br />
1 0COMPARATOR0 1<br />
26 FFLAG5 <br />
1COMPARATOR1<br />
2 PWM 0<br />
1FTACK5 1 FFLAG5 <br />
0 <br />
1COMPARATOR1<br />
1 <br />
1COMPARATOR1<br />
27 FPIN5 <br />
1COMPARATOR1 0<br />
0 1COMPARATOR1 0<br />
1 1COMPARATOR1 1<br />
28 FFLAG6 (CTRL<br />
SOFTFAULT) 2 PWM 0<br />
1FTACK5 1 FFLAG5 <br />
0 <br />
1 <br />
3129 - - 0<br />
6.3.4 PWM <br />
<br />
PWMn 0~7 <br />
(OUTCTL m) PWMn_m OUTm <br />
<br />
OUTCTL <br />
Table 6-6 PWM (OUT CTRL; n=0,1.2) <br />
<br />
0 OUT0 PWMn_0 0<br />
0 0<br />
1 1<br />
1 OUT1 PWMn_1 0<br />
0 0<br />
1 1PWM n_0 <br />
n_1<br />
2 OUT2 PWMn_2 0<br />
0 0<br />
1 1<br />
3 OUT3 PWMn_3 0<br />
0 0<br />
1 1PWM n_2 <br />
n_3<br />
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4 OUT4 PWMn_4 0<br />
0 0<br />
1 1<br />
5 OUT5 PWMn_5 0<br />
0 0<br />
1 1PWM n_4 <br />
n_5<br />
6 OUT6 PWMn_6 0<br />
0 0<br />
1 1<br />
7 OUT7 PWMn_7 0<br />
0 0<br />
1 1PWM n_6 <br />
n_7<br />
8 OUTCTL 0 PWMn_0 0<br />
0 <br />
1 <br />
9 OUTCTL 1 PWMn_1 0<br />
0 <br />
1 <br />
10 OUTCTL 2 PWMn_2 0<br />
0 <br />
1 <br />
11 OUTCTL 3 PWMn_3 0<br />
0 <br />
1 <br />
12 OUTCTL 4 PWMn_4 0<br />
0 <br />
1 <br />
13 OUTCTL 5 PWMn_5 0<br />
0 <br />
1 <br />
14 OUTCTL 6 PWMn_6 0<br />
0 <br />
1 <br />
15 OUTCTL7 PWMn_7 0<br />
0 <br />
1 <br />
31:16 - - 0<br />
6.3.5 PWM <br />
Table 6-7 PWM (CNTR) <br />
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<br />
31:0 CNT - <br />
PWM <br />
PWM <br />
PWMEN 1 0<br />
<br />
6.3.6 PWM <br />
PWM <br />
PWM <br />
LDOK 1 PWM <br />
CMOD <br />
PWM .<br />
Table 6-8 PWM (CMOD;)<br />
<br />
31:0 CMOD - 32 <br />
PWM <br />
0<br />
6.3.7 PWM <br />
32 <br />
PWM <br />
0PWM PWM <br />
0<br />
PWM CMOD<br />
PWM PWM <br />
1<br />
Table 6-9 PWM (VALm, m=0~7) <br />
<br />
31:0 VAL - PWM s 0<br />
6.3.8 PWM <br />
DTIM0 PWM <br />
0 1 <br />
DTIM1 PWM <br />
1 0 <br />
<br />
<br />
PWM PRSC <br />
DT=P × DTIMm – 1 PWM <br />
P PRSC<br />
DTIMm <br />
PWM PRSC<br />
2<br />
DTIMm 5<br />
DT = 2 × 5 - 1 = 9 PWM <br />
<br />
P=1DT=DTIMm<br />
Table 6-10 PWM (DTIMm, m=0,1) <br />
<br />
31:0 DTIMm - <br />
32 <br />
PWM 0xFFFFFFFF<br />
6.3.9 PWM <br />
<br />
PWM DMAP1-2 <br />
1 CNFG WP 1 DMAP1-2 <br />
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XN62Lxxx<br />
Table 6-11: PWM (DMAP1)<br />
1<br />
<br />
0 P0FLTMAP0 0PWM_FAULT0<br />
0 1<br />
0 <br />
1 <br />
1 P0FLTMAP1 1PWM_FAULT1<br />
0 1<br />
0 <br />
1 <br />
2 P0FLTMAP2 2PWM_FAULT2<br />
0 1<br />
0 <br />
1 <br />
3 P0FLTMAP3 3PWM_FAULT3<br />
0 1<br />
0 <br />
1 <br />
4 P0FLTMAP4 0 COMPARATOR0<br />
PWM 0 1<br />
0 <br />
1 <br />
5 P0FLTMAP5 1 COMPARATOR1<br />
PWM 0 1<br />
0 <br />
1 <br />
6 P0FLTMAP6 <br />
PWM 0 1<br />
0 <br />
1 <br />
7 - - 1<br />
15:8 P1FLTMAPn PWM 1 <br />
PWM 0F0FLTMAPn<br />
23:16 P2FLTMAPn PWM 2 <br />
PWM 0F0FLTMAPn<br />
31:24 P3FLTMAPn PWM 3 <br />
PWM 0F0FLTMAPn<br />
0xFF<br />
0xFF<br />
0xFF<br />
Table 6-12: PWM (DMAP1)<br />
2<br />
<br />
7:0 P4FLTMAPn PWM 4 <br />
PWM 0F0FLTMAPn<br />
15:8 P5FLTMAPn PWM 5 <br />
PWM 0F0FLTMAPn<br />
23:16 P6FLTMAPn PWM 6 <br />
PWM 0F0FLTMAPn<br />
31:24 P7FLTMAPn PWM 7 <br />
PWM 0F0FLTMAPn<br />
0xFF<br />
0xFF<br />
0xFF<br />
0xFF<br />
6.3.10 PWM <br />
<br />
PWM CNFG WP 1 <br />
Table 6-13: PWM (CNFG)<br />
<br />
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XN62Lxxx<br />
0 WP PWM <br />
0<br />
CNFG <br />
<br />
DMAP1–2, DTIM, CNFG, CCTRL ENHA <br />
ENHA VLMODE, SWP67, SWP45, SWP23, CCTRL <br />
SWP01 <br />
: CNFG WP 1 <br />
<br />
0 <br />
1 <br />
1 NDEP01 <br />
PWMn 0-1 <br />
0<br />
0 <br />
1 <br />
2 NDEP23 <br />
PWMn 2-3 <br />
0<br />
0 <br />
1 <br />
3 NDEP45 <br />
PWMn 4-5 <br />
0<br />
0 <br />
1 <br />
4 NDEP67 <br />
PWMn 6-7 <br />
0<br />
0 <br />
1 <br />
5 BOTNEG01 <br />
PWMn 1 0<br />
0 <br />
1 <br />
6 BOTNEG23 <br />
PWMn 3 0<br />
0 <br />
1 <br />
7 BOTNEG45 <br />
PWMn 5 0<br />
0 <br />
1 <br />
8 BOTNEG67 <br />
PWMn 7 0<br />
0 <br />
1 <br />
9 TOPNEG01 <br />
PWMn 0 0<br />
0 <br />
1 <br />
10 TOPNEG23 <br />
PWMn 2 0<br />
0 <br />
1 <br />
11 TOPNEG45 <br />
PWMn 4 0<br />
136 www.xinnovatech.com
XN62Lxxx<br />
0 <br />
1 <br />
12 TOPNEG67 <br />
PWMn 6 0<br />
0 <br />
1 <br />
13 EDG <br />
PWMn <br />
0<br />
<br />
0 <br />
1 <br />
31:14 - - 0<br />
6.3.11 PWM <br />
<br />
PWM <br />
ENHA VLMODE, SWP67, SWP45, SWP23 SWP01 <br />
ENHA<br />
<br />
CNFG WP <br />
Table 6-14: PWM (CCTRL , n=0,1.2) <br />
<br />
0 SWP01 ENHA 0 PWM<br />
0-1 0<br />
0 <br />
1 PWM 0-1 <br />
1 SWP23 ENHA 0 <br />
PWM 2-3 0<br />
0 <br />
1 PWM 2-3 <br />
2 SWP45 ENHA 0 <br />
PWM 4-5 0<br />
0 <br />
1 PWM 4-5 <br />
3 SWP67 ENHA 0 <br />
PWM 6-7 0<br />
0 <br />
1 PWM 6-7 <br />
5:4 VLMODE PWM <br />
ENHA 0 <br />
00<br />
00 VAL0~7 <br />
PMW0~7 01 VAL0 <br />
PMW0~5 <br />
10 VAL0 <br />
PMW0~3 <br />
11 VAL0 <br />
PMW0~7 <br />
6 MSK0 PWM 0 0<br />
0 <br />
1 0 <br />
7 MSK1 PWM 1 0<br />
0 <br />
1 1 <br />
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XN62Lxxx<br />
8 MSK2 PWM 2 0<br />
0 <br />
1 2 <br />
9 MSK3 PWM 3 0<br />
0 <br />
1 3 <br />
10 MSK4 PWM 4 0<br />
0 <br />
1 4 <br />
11 MSK5 PWM 5 0<br />
0 <br />
1 5 <br />
12 MSK6 PWM 6 0<br />
0 <br />
1 6 <br />
13 MSK7 PWM 7 0<br />
0 <br />
1 7 <br />
14 - 0<br />
15 ENHA <br />
VLMODE, SWP67, SWP45, SWP23, SWP01<br />
0<br />
<br />
CNFG WP 1 .<br />
0 VLMODE, SWP67, SWP45, SWP23 SWP01 <br />
1 VLMODE, SWP67, SWP45, SWP23 SWP01 <br />
31:16 - - 0<br />
6.3.12 PWM <br />
Table 6-15: PWM (FPORTCTRL , n=0,1.2) <br />
<br />
7:0 FAULTPORT PWM 8 1<br />
0<br />
<br />
8 FAULTVAL0 PWM FPSEL=1 PWM 0 0<br />
0 0<br />
1 1<br />
9 FAULTVAL1 PWM FPSEL=1 PWM 1 0<br />
0 0<br />
1 1<br />
10 FAULTVAL2 PWM FPSEL=1 PWM 2 0<br />
0 0<br />
1 1<br />
11 FAULTVAL3 PWM FPSEL=1 PWM 3 0<br />
0 0<br />
138 www.xinnovatech.com
XN62Lxxx<br />
1 1<br />
12 FAULTVAL4 PWM FPSEL=1 PWM 4 0<br />
0 0<br />
1 1<br />
13 FAULTVAL5 PWM FPSEL=1 PWM 5 0<br />
0 0<br />
1 1<br />
14 FAULTVAL6 PWM FPSEL=1 PWM 6 0<br />
0 0<br />
1 1<br />
15 FAULTVAL7 PWM FPSEL=1 PWM 7 0<br />
0 0<br />
1 1<br />
16 FPSEL0 PWM <br />
FAULTVAL0 PWM 0. 0<br />
0 PWM <br />
1 FAULTVAL0 PWM <br />
17 FPSEL1 PWM <br />
FAULTVAL1 PWM 1. 0<br />
0 PWM <br />
1 FAULTVAL1 PWM <br />
18 FPSEL2 PWM <br />
FAULTVAL2 PWM 2. 0<br />
0 PWM <br />
1 FAULTVAL2 PWM <br />
19 FPSEL3 PWM <br />
FAULTVAL3 PWM 3. 0<br />
0 PWM <br />
1 FAULTVAL3 PWM <br />
20 FPSEL4 PWM <br />
FAULTVAL4 PWM 4. 0<br />
0 PWM <br />
1 FAULTVAL4 PWM <br />
21 FPSEL5 PWM <br />
FAULTVAL5 PWM 5. 0<br />
0 PWM <br />
1 FAULTVAL5 PWM <br />
22 FPSEL6 PWM <br />
FAULTVAL6 PWM 6. 0<br />
0 PWM <br />
1 FAULTVAL6 PWM <br />
23 FPSEL7 PWM <br />
FAULTVAL6 PWM 7. 0<br />
0 PWM <br />
1 FAULTVAL7 PWM <br />
31:24 - - . NA<br />
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6.3.13 PWM <br />
<br />
IPOLm Valm PWM Table 6-16: PWM (ICCTRL, n=0,1.2) <br />
<br />
0 ICC0 PWM 0-1 . 0<br />
0 IPOL0 VAL0 VAL1 <br />
1 PWM <br />
VAL0 PWM <br />
VAL1 1 ICC1 PWM 2-3 . 0<br />
0 IPOL1 VAL2 VAL3 <br />
1 PWM <br />
VAL2 PWM <br />
VAL3 2 ICC2 PWM 4-5 . 0<br />
0 IPOL2 VAL4 VAL5 <br />
1 PWM <br />
VAL4 PWM <br />
VAL5 3 ICC3 PWM 6-7 . 0<br />
0 IPOL3 VAL6 VAL7 <br />
1 PWM <br />
VAL6 PWM <br />
VAL7 4 PAD_EN PWM <br />
PWM <br />
0<br />
PWM <br />
0 <br />
1 <br />
31:5 - - . 0<br />
6.3.14 PWM <br />
<br />
PWM <br />
CNFG WP <br />
WP 0 <br />
Table 6-17: PWM (SCTRL; n=0,1.2) <br />
<br />
1:0 SRC0 PWMn_0/PWMn_1 <br />
OUTCTL0 OUTCTL1 0<br />
( OUT 8,9 ) 1<br />
00 PWM <br />
01 ADC0 LOWLMT0 HILMT0 <br />
HILMT0 0 1 PWMn_0 1PWMn_1 0<br />
LOWLMT0 0 1 PWMn_0 0PWMn_1<br />
10 GPIO0_20 <br />
11 TMRSEL [1:0]<br />
/<br />
0Match0<br />
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XN62Lxxx<br />
<br />
Match 0 <br />
PWMn_0 0PWMn_1 1<br />
PWMn_0 1PWMn_1 0<br />
4:2 SRC1 PWMn_2/PWMn_3 <br />
OUTCTL2 OUTCTL3 0<br />
( OUT 10,11 ) 1<br />
000 PWM <br />
001 ADC0 LOWLMT1 HILMT1 <br />
HILMT1 0 1 PWMn_2 1PWMn_3 0<br />
LOWLMT1 0 1 PWMn_2 0PWMn_ 3 1<br />
010 GPIO0_19 <br />
011 TMRSEL [3:2]<br />
/<br />
0Match0<br />
<br />
Match 0 PWMn_2 0PWMn_3 1<br />
PWMn_2 1PWMn_3 0<br />
1xx<br />
SRC0 <br />
7:5 SRC2 PWMn_4/PWMn_5 <br />
OUTCTL4 OUTCTL5 0<br />
( OUT 12,13 ) 1<br />
000 PWM <br />
001 ADC1 LOWLMT0 HILMT0 <br />
HILMT0 0 1 PWMn_4 1PWMn_5 0<br />
LOWLMT0 0 1 PWMn_4 0PWMn_5 1<br />
010 GPIO0_2 <br />
011 TMRSEL [5:4]<br />
/<br />
0Match0<br />
<br />
Match 0 PWMn_4 0PWMn_5 1<br />
PWMn_4 1PWMn_5 0<br />
1xx<br />
SRC0 <br />
10:8 SRC3 PWMn_6/PWMn_7 <br />
OUTCTL6 OUTCTL7 0<br />
( OUT 14,15 ) 1<br />
000 PWM <br />
001 ADC1 LOWLMT1 HILMT1 <br />
HILMT1 0 1 PWMn_6 1PWMn_7 0<br />
LOWLMT1 0 1 PWMn_6 0PWMn_7 1<br />
010 GPIO0_1 <br />
011 TMRSEL [7:6]<br />
/<br />
0Match0<br />
<br />
Match 0 PWMn_6 0PWMn_7 1<br />
PWMn_6 1PWMn_7 0<br />
1xx<br />
SRC0 <br />
31:11 - - 0<br />
6.3.15 PWM <br />
Table 6-18: PWM TMR (TMRSEL) <br />
<br />
1:0 SRC0TMSEL PWM 0,1 0<br />
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0 TMR32B0 0<br />
1 TMR32B1 0<br />
2 TMR16B0 0<br />
3 TMR16B1 0<br />
3:2 SRC1TMSEL PWM 2,3 0<br />
0 TMR32B0 0<br />
1 TMR32B1 0<br />
2 TMR16B0 0<br />
3 TMR16B1 0<br />
5:4 SRC2TMSEL PWM 4,5 0<br />
0 TMR32B0 0<br />
1 TMR32B1 0<br />
2 TMR16B0 0<br />
3 TMR16B1 0<br />
7:6 SRC3TMSEL PWM 6,7 0<br />
0 TMR32B0 0<br />
1 TMR32B1 0<br />
2 TMR16B0 0<br />
3 TMR16B1 0<br />
31:8 - - 0<br />
6.3.16 PWM <br />
Table 6-19: PWM (PSCR ; n=0,1.2) <br />
<br />
0 CINV0 PWM 0 0<br />
0 CNTR <br />
VAL0<br />
1 CNTR <br />
VAL0<br />
1 CINV1 PWM 1 0<br />
0 CNTR <br />
VAL1<br />
1 CNTR <br />
VAL1<br />
2 CINV2 PWM 2 0<br />
0 CNTR <br />
VAL2<br />
1 CNTR <br />
VAL2<br />
3 CINV3 PWM 3 0<br />
0 CNTR <br />
VAL3<br />
1 CNTR <br />
VAL3<br />
4 CINV4 PWM 4 0<br />
0 CNTR <br />
VAL4<br />
1 CNTR <br />
VAL4<br />
5 CINV5 PWM 5 0<br />
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XN62Lxxx<br />
0 CNTR <br />
VAL5<br />
1 CNTR <br />
VAL5<br />
6 CINV6 PWM 6 0<br />
0 CNTR <br />
VAL6<br />
1 CNTR <br />
VAL6<br />
7 CINV7 PWM 7 0<br />
0 CNTR <br />
VAL7<br />
1 CNTR <br />
VAL7<br />
31:8 - - 0<br />
6.3.17 PWM <br />
Table 6-20: PWM <br />
(CNTRINI) <br />
<br />
31:0 INITVAL PWM <br />
PWM PWM 0<br />
<br />
PWM <br />
6.3.18 PWM <br />
PWM <br />
PWM 0 PWM 1PWM 2 PWM 3… PWM0 PWM1<br />
<br />
Table 5-21: PWM <br />
(DELAYST; n=0.1) <br />
<br />
30:0 DLYTIME 31 <br />
PWM 0<br />
31 TRIG_EN PWM n n+1 0<br />
0 <br />
1 <br />
6.4 <br />
6.4.1 <br />
PWM PWM<br />
PWMn_PCLK (System Clock)12,4,8 CTRL <br />
PRSC <br />
LDOK 1 PWM PWM <br />
.<br />
6.4.2 PWM<br />
PWM <br />
32 <br />
PWM PWM <br />
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6.4.2.1 <br />
PWM Edge<br />
-AlignCenter<br />
-Aligned PWM CNFG <br />
<br />
PSCR CINVm PWM <br />
• VALm PWM <br />
CINVm=0PWM <br />
CINVm=1PWM<br />
<br />
• VALm <br />
PWM <br />
CINVm=0PWM <br />
CINVm=1<br />
PWM <br />
Alignment Reference<br />
Up/Down Counter<br />
Modulus =4<br />
PWM Compare Output<br />
Duty Cycle = 50%<br />
CINVx = 0<br />
CINVx = 1<br />
Figure 6-2: PWM <br />
: <br />
PWM modulu<br />
0 <br />
<br />
6.4.2.2 <br />
PWM <br />
CMOD PWM<br />
/<br />
<br />
<br />
2 PWM <br />
CMOD PWM<br />
<br />
PWM = (PWM ) × (PWM ) × 2<br />
4<br />
3<br />
Up/Down Counter Modulus = 4<br />
PWM Clock Period<br />
2<br />
1<br />
0<br />
PWM Period = 8 x PWM Clock Period<br />
Figure 6-3: PWM <br />
PWM<br />
PWM<br />
1 <br />
PWM <br />
<br />
CMOD PWM <br />
PWM = (PWM ) × (PWM )<br />
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XN62Lxxx<br />
4<br />
3<br />
2<br />
Up Counter Modulus = 4<br />
PWM Clock Period<br />
1<br />
0<br />
PWM Period = 8 x PWM Clock Period<br />
Figure 6-4: PWM <br />
6.4.2.3 <br />
PWM <br />
32 PWM <br />
CINVx=1<br />
<br />
PWM PWM <br />
: PWM <br />
PWM CINVx=0PWM<br />
<br />
CINVx=0<br />
PWM PWM <br />
PWM <br />
0CINVx=0 PWM PWM <br />
CINVx=1<br />
PWM <br />
PWM <br />
Figure 6-5 PWM <br />
2 PWM <br />
PWM <br />
PWM = (PWM ) ) × (PWM<br />
× 2<br />
Up/Down Counter<br />
2<br />
Modulus = 4 1<br />
PWM Value = 0<br />
0/4 = 0%<br />
PWM Value = 1<br />
1/4 = 25%<br />
PWM Value = 2<br />
2/4 = 50%<br />
PWM Value = 3<br />
3/4 = 75%<br />
PWM Value = 4<br />
4/4 = 100%<br />
4<br />
3<br />
0<br />
Figure 6-5: <br />
<br />
Figure 6-6 PWM <br />
PWM <br />
PWM <br />
PWM = (PWM ) )<br />
× (PWM<br />
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XN62Lxxx<br />
Up Counter<br />
2<br />
Modulus = 4 1<br />
PWM Value = 0<br />
0/4 = 0%<br />
PWM Value = 1<br />
1/4 = 25%<br />
PWM Value = 2<br />
2/4 = 50%<br />
PWM Value = 3<br />
3/4 = 75%<br />
PWM Value = 4<br />
4/4 = 100%<br />
4<br />
3<br />
Figure 6-6: <br />
6.4.3 <br />
CNFG INDEPm PWM <br />
INDEPm 1 PWM 0 -1,2-3,4-5,6-7<br />
<br />
PWM <br />
PWM <br />
INDEPm 0 PWM 0 -1,2-3,4-5,6-7<br />
PWM <br />
Figure 6-7 .<br />
VAL 0<br />
Register<br />
VAL 1<br />
Register<br />
PWM CHANNELS 0 AND 1<br />
TOP<br />
BOTTOM<br />
VAL 2<br />
Register<br />
VAL 3<br />
Register<br />
PWM CHANNELS 2 AND 3<br />
TOP<br />
BOTTOM<br />
VAL 4<br />
Register<br />
VAL 5<br />
Register<br />
PWM CHANNELS 4 AND 5<br />
TOP<br />
BOTTOM<br />
VAL 6<br />
Register<br />
VAL 7<br />
Register<br />
PWM CHANNELS 6 AND 7<br />
TOP<br />
BOTTOM<br />
Figure 6-7: <br />
PWM<br />
Figure 6-8 <br />
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XN62Lxxx<br />
PWM<br />
0<br />
PWM<br />
2<br />
PWM<br />
4<br />
AC<br />
Inputs<br />
3-Phase<br />
Load<br />
PWM<br />
1<br />
PWM<br />
3<br />
PWM<br />
5<br />
Figure 6-8:<br />
PWM<br />
<br />
1. <br />
2. <br />
PWM <br />
3. <br />
PWM <br />
6.4.4 <br />
PWM<br />
<br />
Figure 6-9 PWM <br />
PWM <br />
<br />
<br />
<br />
PWM PWM<br />
DTIMx<br />
<br />
PWM <br />
PWM <br />
DTIM0 PWM <br />
DTIM1 PWM <br />
PWM /<br />
PWM<br />
Generator<br />
Current<br />
Status<br />
OUT0<br />
PWM0 &<br />
PWM1<br />
OUT2<br />
PWM2 &<br />
PWM3<br />
OUT4<br />
PWM4 &<br />
PWM5<br />
OUT6<br />
PWM6 &<br />
PWM7<br />
MUX<br />
OUTCLT0<br />
MUX<br />
OUTCLT2<br />
MUX<br />
OUTCLT4<br />
MUX<br />
OUTCLT6<br />
OUT1<br />
Deadtime<br />
Generator<br />
OUT3<br />
Deadtime<br />
Generator<br />
OUT5<br />
Deadtime<br />
Generator<br />
OUT7<br />
Deadtime<br />
Generator<br />
Top/Bottom<br />
Generator<br />
Top/Bottom<br />
Generator<br />
Top/Bottom<br />
Generator<br />
Top/Bottom<br />
Generator<br />
Top(PWM0)<br />
Bottom(PWM1)<br />
Top(PWM2)<br />
Bottom(PWM3)<br />
Top(PWM4)<br />
Bottom(PWM5)<br />
Top(PWM6)<br />
Bottom(PWM7)<br />
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Figure 6-9: <br />
Figure 6-10, Figure 6-11, Figure 6-12 <br />
Modulus = 4<br />
PWM Value = 2<br />
PWM 0, No Deadtime<br />
PWM 1, No Deadtime<br />
PWM 0, Deadtime = 1<br />
PWM 1, Deadtime = 1<br />
Figure 6-10: <br />
Modulus = 3<br />
PWM Value = 1 PWM Value = 1 PWM Value = 3 PWM Value = 3<br />
PWM 0, No Deadtime<br />
PWM 1, No Deadtime<br />
PWM 0, Deadtime = 2<br />
PWM 1, Deadtime = 2<br />
Figure 6-11: <br />
Modulus = 3<br />
PWM<br />
Value = 2<br />
PWM<br />
Value = 3<br />
PWM<br />
Value = 2<br />
PWM<br />
Value = 1<br />
PWM 0, No Deadtime<br />
PWM 1, No Deadtime<br />
PWM 0, Deadtime = 3<br />
PWM 1, Deadtime = 3<br />
Figure 6-12: <br />
6.4.4.1 <br />
<br />
<br />
<br />
<br />
Figure 6-13<br />
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XN62Lxxx<br />
Desired<br />
Load Voltage<br />
Deadtime<br />
PWM To Top<br />
Transistor<br />
V+<br />
Positive<br />
Current Direction<br />
PWM To Bottom<br />
Transistor<br />
Positive Current<br />
Load Voltage<br />
Negative Current<br />
Load Voltage<br />
Negative<br />
Current Direction<br />
Figure 6-13: <br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
PWM<br />
<br />
<br />
VALm<br />
<br />
<br />
• ICCTRL ICC 0IPOL n <br />
• ICCTRL ICC 1<br />
VALn <br />
• <br />
VALn • <br />
VALn : <br />
ICCn 0 CTRL IPOL0–IPOL2 <br />
/<br />
PWM <br />
Table 6-21: / <br />
<br />
IPOL0<br />
IPOL1<br />
IPOL2<br />
IPOL3<br />
0 PWMnVAL0 PWMn_0/ PWMn_1 <br />
1 PWMnVAL1 PWMn_0/ PWMn_1 <br />
0 PWMnVAL2 PWMn_2/ PWMn_3 <br />
1 PWMnVAL3 PWMn_2/ PWMn_3 <br />
0 PWMnVAL4 PWMn_4/ PWMn_5 <br />
1 PWMnVAL5 PWMn_4/ PWMn_5 <br />
0 PWMnVAL6 PWMn_6/ PWMn_7 <br />
1 PWMnVAL7 PWMn_6/ PWMn_7 <br />
: IPOLn <br />
PWM <br />
PWM <br />
IPOLn PWM <br />
LDOK IPOL<br />
n <br />
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XN62Lxxx<br />
<br />
Figure 6-14 Figure 6-15 <br />
Deadtime<br />
Desired Load Voltage<br />
Top PWM<br />
Bottom PWM<br />
Load Voltage<br />
Figure 6-14: <br />
Deadtime<br />
Desired Load Voltage<br />
Top PWM<br />
Bottom PWM<br />
Load Voltage<br />
Figure 6-15: <br />
6.4.5 PWM<br />
PWM<br />
PWM<br />
<br />
PWM <br />
PWM PWM <br />
PWM <br />
PWM PWM <br />
PWM <br />
PWM Table 6-22: ICCn / <br />
<br />
ICC0<br />
ICC1<br />
ICC2<br />
ICC3<br />
0 IPOL0 PWMn_0/ PWMn_1 <br />
1 PWM <br />
PWMn_0/ PWMn_1 <br />
0 IPOL1 PWMn_2/ PWMn_3 <br />
1 PWM <br />
PWMn_2/ PWMn_3 <br />
0 IPOL2 PWMn_4/ PWMn_5 <br />
1 PWM <br />
PWMn_4/ PWMn_5 <br />
0 IPOL3 PWMn_6/ PWMn_7 <br />
1 PWM <br />
PWMn_6/ PWMn_7 <br />
: ICCTRL ICCn PWM <br />
PWM 150 www.xinnovatech.com
XN62Lxxx<br />
4<br />
3<br />
2<br />
Up/Down Counter<br />
Modulus =4<br />
Even PWM<br />
Value = 1<br />
Odd PWM<br />
Value = 3<br />
1<br />
0<br />
Even PWM<br />
Value<br />
Odd PWM<br />
Value<br />
Even PWM<br />
Value<br />
Odd PWM<br />
Value<br />
Even PWM<br />
Value = 3<br />
Odd PWM<br />
Value = 1<br />
Figure 6-16: – PWM <br />
6.4.6 PWM <br />
PWM <br />
1. TOPNEGnn PWM PWMn_0, PWMn_2, PWMn_4 PWMn_6<br />
TOPNEGnn <br />
2. BOTNEGnn PWM PWMn_1, PWMn_3, PWMn_5 PWMn_7<br />
BOTNEGnn <br />
TOPNEGnn BOTNEGnn <br />
CNFG Figure 6-17<br />
Center-Aligned<br />
Positive PWM Output Polarity<br />
Edge-Aligned<br />
Positive PWM Output Polarity<br />
Up/Down Counter<br />
Modulus = 4<br />
PWM = 0<br />
PWM = 1<br />
PWM = 2<br />
PWM = 3<br />
PWM = 4<br />
Up Counter<br />
Modulus = 4<br />
PWM = 0<br />
PWM = 1<br />
PWM = 2<br />
PWM = 3<br />
PWM = 4<br />
Center-Aligned<br />
Negative PWM Output Polarity<br />
Edge-Aligned<br />
Negative PWM Output Polarity<br />
Up/Down Counter<br />
Modulus = 4<br />
PWM = 0<br />
PWM = 1<br />
PWM = 2<br />
PWM = 3<br />
PWM = 4<br />
Up Counter<br />
Modulus = 4<br />
PWM = 0<br />
PWM = 1<br />
PWM = 2<br />
PWM = 3<br />
PWM = 4<br />
Figure 6-17: PWM <br />
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6.4.7 <br />
(OUTCTRL<br />
n) PWM <br />
PWM <br />
OUTCTRLm=1 OUTm PWMn_m /<br />
OUTm <br />
PWM OUTCTRL<br />
m OUTm <br />
PWM <br />
OUT <br />
<br />
TOPNEGmm BOTNEGmm <br />
Modulus = 4<br />
PWM Value = 2<br />
Deadtime = 1<br />
PWM 0 Generator<br />
PWM 1 Generator<br />
OUTCTL0<br />
OUT0<br />
OUT1<br />
PWM 0 with Deadtime<br />
PWM 1 with Deadtime<br />
OUTCTL0 is Cleared<br />
Toggling OUT0 with OUTCTL0<br />
Set<br />
Toggling OUT1 with<br />
OUTCTL0 Set and<br />
OUT0 Clear<br />
Setting OUTCTL0 with OUT0 Set<br />
Figure 6-18: <br />
6.4.8 PWM<br />
6.4.8.1 <br />
LDOK <br />
PWM <br />
• PWM (CTRL) PRSC <br />
• (CMOD) PWM <br />
• VALm <br />
PWM <br />
LDOK <br />
PWM LDOK <br />
PWM<br />
<br />
PWM <br />
LDOK 0<br />
6.4.8.2 <br />
CTRL LFQ <br />
PWM 1 16 <br />
PWM <br />
LDOK LDFQ CTRL<br />
HALF <br />
HALF <br />
HALF <br />
.<br />
:modulu<br />
PWM <br />
<br />
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XN62Lxxx<br />
Up/Down<br />
Counter<br />
Reload<br />
Change<br />
Reload<br />
Frequency<br />
To Every<br />
Two Opportunities<br />
To Every<br />
Four Opportunities<br />
To Every<br />
Opportunities<br />
Figure 6-19: <br />
Up/Down<br />
Counter<br />
Reload<br />
Change<br />
Reload<br />
Frequency<br />
To Every<br />
Two Half<br />
Opportunities<br />
To Every<br />
Four Half<br />
Opportunities<br />
To Every Half<br />
Opportunities<br />
To Every<br />
Two Half<br />
Opportunities<br />
Figure 6-20: <br />
6.4.8.3 <br />
PWM <br />
LDOK CTRL<br />
PWM (PWMF) <br />
(PWMRIE) PWMF <br />
PWMF <br />
PWMF 0 PWMF Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle<br />
Up/Down<br />
Counter<br />
LDOK = 1<br />
Modulus = 3<br />
PWM Value = 1<br />
PWMF = 1<br />
0<br />
3<br />
2<br />
1<br />
1<br />
3<br />
2<br />
1<br />
0<br />
3<br />
1<br />
1<br />
PWM<br />
Figure 6-21: PWM <br />
Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle<br />
Up/Down<br />
Counter<br />
0<br />
1<br />
3<br />
2 2 2<br />
1 1 1 1 1<br />
0 0 0 0<br />
LDOK = 1<br />
Modulus = 2<br />
PWM Value = 1<br />
PWMF = 1<br />
1<br />
3<br />
1<br />
1<br />
1<br />
2<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
0<br />
2<br />
1<br />
1<br />
PWM<br />
Figure 6-22: PWM <br />
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Half = 1, LDFQ[3:0] = 0000 = Reload Every Half Cycle<br />
Up/Down<br />
Counter<br />
LDOK = 1<br />
Modulus = 3<br />
PWM Value = 1<br />
PWMF = 1<br />
1<br />
3<br />
2<br />
1<br />
0<br />
3<br />
2<br />
1<br />
0<br />
3<br />
2<br />
1<br />
1<br />
3<br />
1<br />
1<br />
1<br />
3<br />
3<br />
1<br />
0<br />
3<br />
3<br />
1<br />
1<br />
3<br />
1<br />
1<br />
PWM<br />
Figure 6-23: PWM <br />
<br />
Half = 1, LDFQ[3:0] = 0000 = Reload Every Half Cycle<br />
Up/Down<br />
Counter<br />
LDOK = 1<br />
Modulus = 2<br />
PWM Value = 1<br />
PWMF = 1<br />
0<br />
2<br />
1<br />
1<br />
0<br />
2<br />
1<br />
1<br />
1<br />
4<br />
1<br />
1<br />
0<br />
4<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
0<br />
2<br />
1<br />
1<br />
1<br />
4<br />
1<br />
1<br />
PWM<br />
Figure 6-24: PWM <br />
<br />
LDFQ[3:0] = 0000 = Reload Every Cycle<br />
Up only<br />
Counter<br />
LDOK = 1<br />
Modulus = 3<br />
PWM Value = 1<br />
PWMF = 1<br />
0<br />
3<br />
2<br />
1<br />
1<br />
3<br />
2<br />
1<br />
0<br />
3<br />
1<br />
1<br />
0<br />
3<br />
1<br />
1<br />
PWM<br />
Figure 6-25: PWM <br />
154 www.xinnovatech.com
XN62Lxxx<br />
LDFQ[3:0] = 0000 = Reload Every Cycle<br />
Up only<br />
Counter<br />
LDOK = 1<br />
Modulus = 3<br />
PWM Value = 2<br />
PWMF = 1<br />
1<br />
4<br />
2<br />
1<br />
1<br />
2<br />
2<br />
1<br />
0<br />
1<br />
2<br />
1<br />
PWM<br />
Figure 6-26: PWM <br />
<br />
6.4.8.4 <br />
PWM <br />
LDOK PWM<br />
<br />
6.4.8.5 PWM<br />
PWMEN <br />
LDOK LDOK=1PWMEN PWM <br />
PWMF <br />
PWMF <br />
PWMRIE <br />
IPOLn s ICCn <br />
PWM <br />
PWM <br />
: PWMPWMEN PWMF LDOK 1<br />
PWM PWMRIE <br />
LDOK <br />
PWM PWM 1PWM 1 <br />
PWMEN <br />
<br />
LDOK ,PWM<br />
PWMEN OUTCTLm <br />
<br />
PWM<br />
Operation Clock<br />
PWM<br />
Bit<br />
PWM<br />
Pins<br />
HI-Z<br />
Active<br />
HI-Z<br />
Figure 6-27: PWMEN PWM (OUTCTL0<br />
-5 = 0)<br />
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XN62Lxxx<br />
PWM<br />
Operation Clock<br />
PWM<br />
Bit<br />
PWM<br />
Pins<br />
HI-Z<br />
Active<br />
HI-Z<br />
Figure 6-28: PWMEN PWM (OUTCTL0,2,4 = 0)<br />
PWMEN :<br />
• PWMn <br />
OUTCTLn=1<br />
• PWM <br />
• PWM <br />
0<br />
• PWMF <br />
• <br />
• <br />
OUTCTLn=1<br />
• <br />
6.4.9 <br />
PWM <br />
PWM <br />
FCTRL <br />
0 1 <br />
PWM <br />
PWM <br />
PWM <br />
PWM <br />
DMAP1–2 7 <br />
PWM 0~7 <br />
PWM <br />
<br />
PWM <br />
P0FLTMAP3 P0FLTMAP2 P0FLTMAP1 P0FLTMAP0<br />
Fault 0<br />
Fault 1<br />
Fault 2<br />
Fault 3<br />
Disable PWM Pin 0<br />
Fault 4<br />
Fault 5<br />
Fault 6<br />
P0FLTMAP4<br />
P0FLTMAP5<br />
P0FLTMAP6<br />
Figure 6-29: -PWMn_0<br />
156 www.xinnovatech.com
XN62Lxxx<br />
Table 6-23: <br />
PWM <br />
PWMn_0<br />
PWMn_1<br />
PWMn_2<br />
PWMn_3<br />
PWMn_4<br />
PWMn_5<br />
PWMn_6<br />
PWMn_7<br />
<br />
DISMAP0[7:0]<br />
DISMAP0[15:8]<br />
DISMAP0[23:16]<br />
DISMAP0[31:24]<br />
DISMAP1[7:0]<br />
DISMAP1[15:8]<br />
DISMAP1[23:16]<br />
DISMAP1[31:24]<br />
6.4.9.1 <br />
XN12L 4 <br />
PWM_FAULT0 ~ PWM_FAULT3<br />
<br />
<br />
PWM <br />
FFLAGm FPINm FPINm <br />
<br />
PWM<br />
1FTACKm FFLAGm FIEm, PWM_FAULTn<br />
FFLAG<br />
m <br />
• 1 FTACKm FFLAGm <br />
• 0 FIEm <br />
• <br />
6.4.9.2 <br />
<br />
FMODEm PWM_FAULTn <br />
PWM <br />
PWM<br />
PWM <br />
Figure 6-30FMODEm <br />
FFLAGm <br />
PWM PWM Output<br />
Fault Input<br />
PWM Enabled Disabled Enabled PWM Disabled PWM Enabled<br />
Figure 6-30: <br />
6.4.9.3 <br />
<br />
0, 2, 4, 5, 6 <br />
FFLAG PWM<br />
<br />
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XN62Lxxx<br />
<br />
PWM Figure 6-31 1, 3 <br />
FFLAGm <br />
PWM <br />
Figure 6-32<br />
Fault 0<br />
Or Fault 2<br />
PWMS Enabled PWMS Disabled PWMS Enabled PWMS Disabled<br />
FFLAGn<br />
Cleared<br />
Figure 6-31: <br />
0<br />
Fault 1<br />
Or Fault 3<br />
PWMS Enabled PWMS Disabled PWMS Enabled<br />
FFLAGn<br />
Cleared<br />
Figure 6-32: <br />
1<br />
• PWM <br />
PWM <br />
PWM <br />
• OUTCTL<br />
m 1<br />
PWM PWMEN=1<br />
<br />
PWM PWMEN=0<br />
OUTm PWM <br />
PWM <br />
<br />
6.4.10 <br />
PWM :<br />
• (PWMF)—PWMF PWM <br />
(PWMRIE) PWMF PWMF<br />
PWMRIE PWM <br />
(CTRL)<br />
• (FFLAG0 –FFLAG6)— FFLAGm PWM_FAULTn <br />
1 FIE0–FIE6 <br />
FFLAGm <br />
FFLAG0–FFLAG6 (FLTAC<br />
FIE0–FIE6 FCTRL<br />
158 www.xinnovatech.com
XN62Lxxx<br />
7 GPIO<br />
7.1 <br />
XN62L 55 GPIO <br />
• <br />
• <br />
• <br />
• <br />
• <br />
• <br />
• GPIO .<br />
7.2 <br />
Table 7-1: GPIO <br />
GPIO LQFP48 LQFP64 <br />
GPIO0 PIO0_0 ~ PIO0_31 31:0 <br />
GPIO1 PIO1_0 ~ PIO1_6 6:0 <br />
GPIO2 PIO2_0 ~ PIO2_15 15:0 <br />
7.3 GPIO<br />
GPIO 3 : Port0, Port2<br />
Port1<br />
GPIO <br />
• Port 0: GPIO0<br />
0 ~ 31<br />
• Port 1: GPIO1<br />
0 ~ 6 7 ~ 31 <br />
• Port 2: GPIO2<br />
0 ~ 15 16 ~ 31 <br />
Table 7-2: <br />
: GPIO ( port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000)<br />
<br />
MASK R/W 0x000 <br />
PIN, 0x0000 OUT, SET, CLR, 0000 NOT<br />
PIN R 0x004 <br />
. <br />
OUT R/W 0x008 . 0x0000 0000<br />
SET W 0x00C <br />
. NA<br />
CLR W 0x010 <br />
. NA<br />
NOT W 0x014 <br />
. 0x0000 0000<br />
DIR R/W 0x020 <br />
. 0x0000 0000<br />
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XN62Lxxx<br />
IS R/W 0x024 <br />
. 0x0000 0000<br />
IBE R/W 0x028 <br />
. 0x0000 0000<br />
IEV R/W 0x02C <br />
. 0x0000 0000<br />
IE R/W 0x030 <br />
. 0x0000 0000<br />
RIS R 0x034 <br />
. 0x0000 0000<br />
MIS R 0x038 <br />
. 0x0000 0000<br />
IC W 0x03C <br />
. 0x0000 0000<br />
7.3.1 GPIO <br />
/<br />
PINOUTSETCLR NOT<br />
MASK <br />
0<br />
<br />
0 OUTSETCLR NOT <br />
<br />
PIN <br />
OUT <br />
1 OUTSETCLR NOT <br />
0<br />
OUT <br />
Table 7-3: GPIO <br />
(MASK - 0x5000 0000 (GPIO0), 0x5001 0000 (GPIO1), 0x5002 0000 (GPIO2)) <br />
<br />
x (31~0) MASKx GPIO PIOn_x <br />
0x0<br />
0 <br />
1 <br />
7.3.2 GPIO <br />
<br />
<br />
GPIO <br />
GPIO GPIO /<br />
<br />
PIN <br />
ADC PIN<br />
MASK <br />
<br />
0<br />
Table 7-4: GPIO <br />
(PIN - 0x5000 0004 (GPIO0), 0x5001 0004 (GPIO1);0x5002 0004 (GPIO2)) <br />
<br />
x (31~0) PINx GPIO PIOn_x . 0<br />
0 <br />
1 <br />
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XN62Lxxx<br />
7.3.3 GPIO <br />
<br />
0 1 <br />
GPIO <br />
GPIO OUT <br />
MASK GPIO <br />
MASK SET<br />
CLR NOT OUT <br />
OUT Table 7-5: GPIO <br />
(OUT - 0x5000 0008 (GPIO0), 0x5001 0008 (GPIO1), 0x5002 0008 (GPIO2)) <br />
<br />
x (31~0) OUTx GPIO PIOn_x . 0<br />
0 : GPIO .<br />
: GPIO <br />
1 : GPIO.<br />
: <br />
7.3.4 GPIO<br />
<br />
DIR <br />
GPIO <br />
IOCONFIG <br />
GPIO <br />
1 <br />
0 GPIO <br />
GPIO SET <br />
<br />
SET MASK <br />
Table 7-6: GPIO <br />
(SET - 0x5000 000C (GPIO0), 0x5001 000C (GPIO1), 0x5002 000C (GPIO2)) <br />
<br />
x (31~0) SETx GPIO PIOn_x <br />
:<br />
0<br />
0 = <br />
1 = GPIO <br />
7.3.5 GPIO <br />
<br />
DIR <br />
GPIO <br />
IOCONFIG <br />
GPIO <br />
1 <br />
0 GPIO <br />
GPIO CLR <br />
<br />
CLR MASK <br />
Table 7-7: GPIO <br />
(CLR - 0x5000 0010 (GPIO0), 0x5000 1010 (GPIO1), 0x5002 0010 (GPIO2)) <br />
<br />
x (31~0) CLEARx GPIO PIOn_x <br />
:<br />
0<br />
0 = <br />
1 = GPIO <br />
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XN62Lxxx<br />
7.3.6 GPIO <br />
<br />
DIR <br />
GPIO <br />
IOCONFIG <br />
GPIO <br />
1 <br />
0 GPIO <br />
GPIO NOT <br />
<br />
NOT <br />
MASK <br />
Table 7-8: GPIO (NOT - 0x5000 0014 (GPIO0), 0x5001 0014 (GPIO1), 0x5002 0014 (GPIO2)) <br />
<br />
x (31~0) NOT GPIO PIOn_x <br />
:<br />
0<br />
0 = <br />
1 = GPIO <br />
7.3.7 GPIO <br />
Table 7-9: GPIO <br />
(DIR - 0x5000 0020 (GPIO0), 0x5001 0020 (GPIO1), 0x5002 0020 (GPIO2)) <br />
<br />
x (31~0) IOx GPIO PIOn_x 0<br />
0 GPIO PIOn_x <br />
1 GPIO PIOn_x <br />
7.3.8 GPIO <br />
Table 7-10: GPIO <br />
(IS - 0x5000 0024 (GPIO0), 0x5001 0024 (GPIO1), 0x5002 0024 (GPIO2)) <br />
<br />
x (31~0) ISENSEx PIOn_x 0<br />
0 PIOn_x <br />
1 PIOn_x <br />
7.3.9 GPIO<br />
Table 7-11: GPIO <br />
(IBE - 0x5000 0028 (GPIO0), 0x5001 0028 (GPIO1), 0x5002 0028 (GPIO2)) <br />
<br />
x (31~0) IBEx PIOn_x / 0<br />
0 PIOn_x <br />
IEV 1 PIOn_x <br />
7.3.10 GPIO <br />
Table 7-12: GPIO <br />
(IEV - 0x5000 002C (GPIO0), 0x5001 002C (GPIO1), 0x5002 002C (GPIO2)) <br />
<br />
x (31~0) IEVx PIOn_x 0<br />
0 .<br />
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XN62Lxxx<br />
1 .<br />
7.3.11 GPIO <br />
lE <br />
Table 7-13: GPIO <br />
(IE - 0x5000 0030, 0x5001 0030 (GPIO1),0x5002 0030 (GPIO2)) <br />
<br />
x (31~0) MASKx <br />
PIOn_x 0<br />
0 PIOn_x <br />
1 PIOn_x <br />
7.3.12 GPIO <br />
lRS <br />
IE 0 <br />
Table 7-14: GPIO <br />
(RIS - 0x5000 0034 (GPIO0), 0x5001 0034 (GPIO1), 0x5002 0034 (GPIO2)) <br />
<br />
x (31~0) RAWSTx 0<br />
0 <br />
PIOn_x <br />
1 PIOn_x <br />
7.3.13 GPIO<br />
MIS <br />
MIS<br />
<br />
Table 7-15: GPIO <br />
(MIS - 0x5000 0038 (GPIO0), 0x5001 0038 (GPIO1), 0x5002 0038 (GPIO2)) <br />
<br />
x (31~0) INTSx PIOn_x 0<br />
0 PIOn_x <br />
1 PIOn_x <br />
7.3.14 GPIO<br />
Table 7-16: GPIO <br />
(IC - 0x5000 003C, 0x5001 003C (GPIO1), 0x5002 003C (GPIO2)) <br />
<br />
x (31~0) CLRx PIOn_x 0<br />
0 0 <br />
1 1 <br />
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XN62Lxxx<br />
8 16 /<br />
8.1 <br />
XN62L <br />
16 / /<br />
SYSAHBCLKDIV <br />
SYSAHBCLKDIV /<br />
<br />
• <br />
16 /<br />
• /<br />
:<br />
– <br />
– <br />
– <br />
– <br />
– <br />
• 16 <br />
• 4 16 :<br />
– <br />
– <br />
– <br />
• :<br />
– <br />
– .<br />
– .<br />
164 www.xinnovatech.com
XN62Lxxx<br />
CAPTURE REGISTER 3<br />
CAPTURE REGISTER 2<br />
CAPTURE GEGISTER 1<br />
CAPTURE REGISTER 0<br />
MATCH REGISTER 3<br />
MATCH REGISTER 2<br />
MATCH REGISTER 1<br />
MATCH REGISTER 0<br />
CAPTURE CONTROL REGISTER<br />
MATCH CONTROL REGISTER<br />
ENTERNAL MATCH REGISTER<br />
INTERRUPT REGISTER<br />
CONTROL<br />
=<br />
=<br />
LOAD[3:0]<br />
=<br />
=<br />
MAT[1:0]<br />
INTERRUPT<br />
CAP[3:0]<br />
TIMER CONTROL<br />
REGISTER<br />
Reset/Enable<br />
TIMER COUNTER<br />
+ -<br />
COUNT/<br />
Edge CNT<br />
QUAD<br />
CNT<br />
GATE<br />
CNT<br />
TRIGGER<br />
CNT<br />
SIGNED<br />
CNT<br />
PRI<br />
SEC<br />
SOURCE SEL<br />
MAXVAL<br />
PRESCALE REGISTER<br />
PRESCALE<br />
COUNTER<br />
CAP[3:0]<br />
Other C16B MAT<br />
C32B MAT<br />
PCLK<br />
Figure 8-1: 16 /<br />
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XN62Lxxx<br />
8.2 <br />
16 / <br />
Table 8-1: 16- /<br />
<br />
CT16B0_CAP[1:0]<br />
CT16B1_CAP[1:0]<br />
CT16B0_MAT[1:0]<br />
CT16B1_MAT[1:0]<br />
<br />
<br />
:<br />
<br />
CT16B0/1 <br />
:<br />
CT16B0/1 <br />
(MR1:0) TC <br />
<br />
EMR PWMCON <br />
2,3<br />
8.3 <br />
Table 8-2: 16 / <br />
(CT16B0 0x4001 0000; CT16B1 0x4001 4000)<br />
<br />
IR R/W 0x000 /<br />
. 0<br />
TCR R/W 0x004 <br />
TCR <br />
0<br />
<br />
TC R/W 0x008 <br />
PCLK 1. TCR 0<br />
<br />
PR R/W 0x00C <br />
PC <br />
TC PC 0<br />
PC R/W 0x010 <br />
16 <br />
PC PR 0<br />
TC 1PC <br />
MCR R/W 0x014 <br />
MCR <br />
TC 0<br />
MR0 R/W 0x018 0 TC <br />
MR0 TC <br />
0<br />
TC <br />
MR1 R/W 0x01C 1<br />
MR0 0<br />
MR2 R/W 0x020 2<br />
MR0 <br />
0<br />
MR3 R/W 0x024 3<br />
MR0 <br />
0<br />
CCR R/W 0x028 CC<br />
TC 0<br />
<br />
CR0 RO 0x02C <br />
0CR0 CT16Bn_CAP0 <br />
TC 0<br />
CR1 RO 0x030 <br />
1CR0 CT16Bn_CAP1 <br />
TC 0<br />
CR2 RO 0x034 <br />
2CR0 CT16Bn_CAP2 <br />
TC 0<br />
CR3 RO 0x038 <br />
3CR0 CT16Bn_CAP3 <br />
TC 0<br />
EMR R/W 0x03C <br />
EMR <br />
0<br />
CT16B0_MAT[1:0] CT16B1_MAT[1:0].<br />
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XN62Lxxx<br />
- - 0x040 - 0x06C -<br />
CTCR R/W 0x070 <br />
CTCR <br />
0<br />
8.3.1 <br />
<br />
4 <br />
2 <br />
IR <br />
IR 1 <br />
0 <br />
DMA Table 8-3: (IR, 0x4001 0000 (CT16B0) 0x4001 4000 (CT16B1)) <br />
<br />
0 MR0INT 0 0<br />
1 MR1INT 1 0<br />
2 MR2INT 2 0<br />
3 MR3INT 3 0<br />
4 CR0INT 0 0<br />
5 CR1INT 1 0<br />
6 CR2INT 2 0<br />
7 CR3INT 3 0<br />
31:8 - -<br />
8.3.2 <br />
/<br />
Table 8-4: <br />
(TCR, 0x4001 0004 (CT16B0) 0x4001 4004 (CT16B1)) <br />
<br />
0 CEN 0<br />
0 <br />
1 <br />
1 CRST 0<br />
0 .<br />
1 <br />
PCLK <br />
TCR <br />
31: 2 - - . NA<br />
8.3.3 <br />
<br />
PC 16 <br />
TC <br />
0x0000 FFFF 0x0000 0000<br />
Table 8-5: <br />
(TC, 0x4001 0008 (CT16B0) 0x4001 4008 (CT16B1)) <br />
<br />
15:0 TC . 0<br />
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XN62Lxxx<br />
31:16 - . - NA<br />
8.3.4 <br />
16 <br />
Table 8-6: (PR, <br />
0x4001 000C (CT16B0) 0x4001 400C (CT16B1)) <br />
<br />
15:0 PCVAL . 0<br />
31:16 - . -<br />
8.3.5 <br />
16 <br />
PCLK <br />
<br />
PCLK <br />
PCLK TC PR = 0 <br />
PCLK <br />
PR = 1 2 PCLK .<br />
Table 8-7: <br />
(PC, 0x4001 0010 (CT16B0) 0x4001 4010 (CT16B1)) <br />
<br />
15:0 PC <br />
. 0<br />
31:16 - . -<br />
8.3.6 <br />
<br />
Table 8-8: <br />
(MCR, 0x4001 0014 (CT16B0) 0x4001 4014 (CT16B1)) <br />
<br />
0 MR0I MR0 TC 0<br />
1 <br />
0 <br />
1 MR0R MR0 TC TC 0<br />
1 <br />
0 <br />
2 MR0S MR0 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
3 MR1I MR1 TC 0<br />
1 <br />
0 <br />
4 MR1R MR1 TC TC 0<br />
1 <br />
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XN62Lxxx<br />
0 <br />
5 MR1S MR1 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
6 MR2I MR2 TC 0<br />
1 <br />
0 <br />
7 MR2R MR2 TC TC 0<br />
1 <br />
0 <br />
8 MR2S MR2 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
9 MR3I MR3 TC 0<br />
1 <br />
0 <br />
10 MR3R MR3 TC TC 0<br />
1 <br />
0 <br />
11 MR3S MR3 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
31:12 . NA<br />
8.3.7 <br />
<br />
<br />
MCR Table 8-9: s (MR0 ~ 3, 0x4001 0018 ~24 (CT16B0) 0x4001 4018~24 (CT16B1)) <br />
<br />
15:0 MATCH . 0<br />
31:16 - . NA<br />
8.3.8 <br />
/<br />
<br />
<br />
“n” 0 1 2 3 “n”<br />
0<br />
1 0 CT16B0 1 CT16B1<br />
Table 8-2: <br />
(CCR, 0x4001 0028 (CT16B0) 0x4001 4028 (CT16B1)) <br />
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XN62Lxxx<br />
<br />
0 CAP0RE CT16Bn_CAP0 <br />
CT16Bn_CAP0 0 1 0<br />
1 <br />
0 <br />
CR0 TC <br />
1 CAP0FE CT16Bn_CAP0 <br />
CT16Bn_CAP0 1 0 0<br />
1 <br />
0 <br />
CR0 TC <br />
2 CAP0I CT16Bn_CAP0 <br />
CT16Bn_CAP0 <br />
CR0 0<br />
1 <br />
0 <br />
<br />
3 CAP1RE CT16Bn_CAP1 <br />
CT16Bn_CAP1 0 1 0<br />
1 <br />
0 <br />
CR1 TC <br />
4 CAP1FE CT16Bn_CAP1 <br />
CT16Bn_CAP1 1 0 0<br />
1 <br />
0 <br />
CR1 TC <br />
5 CAP1I CT16Bn_CAP1 <br />
CT16Bn_CAP0 <br />
CR1 0<br />
1 <br />
0 <br />
<br />
6 CAP2RE 0 <br />
0 0 1 <br />
CR2 0<br />
1 <br />
0 <br />
TC <br />
7 CAP2FE 0 <br />
0 1 0 <br />
CR2 0<br />
1 <br />
0 <br />
TC <br />
8 CAP2I 0 <br />
0 <br />
CR2 0<br />
1 <br />
0 <br />
<br />
9 CAP3RE 1 <br />
1 0 1 <br />
CR3 0<br />
1 <br />
TC <br />
170 www.xinnovatech.com
XN62Lxxx<br />
0 <br />
10 CAP3FE 1 <br />
1 1 0 <br />
CR3 0<br />
1 <br />
0 <br />
TC <br />
11 CAP3I 1 <br />
1 <br />
CR3 0<br />
1 <br />
0 <br />
<br />
31:12 - NA<br />
8.3.9 <br />
<br />
<br />
Table 8-3: (CR0<br />
~ 3, 0x4001 002C ~ 38 (CT16B0) 0x4001 402C ~ 38 (CT16B1)) <br />
<br />
15:0 CAP 0<br />
31:16 - . NA<br />
8.3.10 <br />
<br />
CT16Bn_MAT[1:0] <br />
0 1 DMA <br />
Table 8-4: <br />
(EMR, 0x4001 003C (CT16B0) 0x4001 403C (CT16B1)) <br />
<br />
0 EM0 0<br />
CT16B0_MAT0/CT16B1_MAT0 <br />
0<br />
<br />
TC MR0 <br />
<br />
EMR[5:4] <br />
IOCON<br />
0=<br />
1= <br />
CT16B0_MAT0/CT16B1_MAT0 <br />
1 EM1 1<br />
CT16B0_MAT1/CT16B1_MAT1 <br />
0<br />
<br />
TC MR1 <br />
<br />
EMR[7:6] <br />
IOCON<br />
0=<br />
1= <br />
CT16B0_MAT0/CT16B1_MAT0 <br />
2 EM2 2<br />
2 TC MR2 <br />
0<br />
<br />
EMR[9:8] <br />
www.xinnovatech.com 171
XN62Lxxx<br />
3 EM3 3<br />
3 <br />
TC MR3 <br />
0<br />
<br />
EMR[11:10] <br />
5:4 EMC0 <br />
0<br />
0 00<br />
00 <br />
01 /<br />
<br />
CT16Bn_MAT0 <br />
<br />
10 /<br />
1 <br />
CT16Bn_MAT0 <br />
<br />
11 <br />
/ 7:6 EMC1 <br />
1<br />
1 00<br />
00 <br />
01 /<br />
<br />
CT16Bn_MAT1 <br />
<br />
10 /<br />
1 <br />
CT16Bn_MAT1 <br />
<br />
11 <br />
/ 9:8 EMC2 <br />
2<br />
3 00<br />
00 <br />
01 /<br />
<br />
CT16Bn_MAT2 <br />
<br />
10 /<br />
1 <br />
CT16Bn_MAT2 <br />
<br />
11 <br />
/ 11: 10 EMC3 <br />
3<br />
3 00<br />
00 <br />
01 /<br />
<br />
CT16Bn_MAT3 <br />
<br />
10 /<br />
1 <br />
CT16Bn_MAT3 <br />
<br />
11 <br />
/ 31: 12 - - . NA<br />
8.3.11 <br />
(CTCR)<br />
<br />
<br />
PCLK CTCR<br />
3:2 CAP <br />
CAP <br />
CAP <br />
CTCR 1:0 <br />
172 www.xinnovatech.com
XN62Lxxx<br />
<br />
PCLK CAP <br />
CAP <br />
PCLK <br />
CAP /<br />
<br />
1/PCLK<br />
<br />
7:4 -<br />
- <br />
CAP <br />
<br />
<br />
Table 8-5: <br />
(CTCR, 0x4001 0070 (CT16B0) 0x4001 4070 (CT16B1)) <br />
<br />
2:0 CTM / <br />
PCLK 00<br />
(PC) <br />
PC (TC)<br />
<br />
CTCR (CCR)<br />
2:0 000<br />
000 <br />
PCLK 001 TC<br />
11:8 CAP <br />
010 TC<br />
11:8 CAP <br />
011 TC<br />
11:8 CAP <br />
100 <br />
101 <br />
110 <br />
111 <br />
3 - - <br />
4 ENCC 1 7:5 - <br />
0<br />
7:5 SELCC 4 1 <br />
000<br />
4 <br />
000 CAP0 <br />
4 001 CAP0 <br />
4 010 CAP1 <br />
4 011 CAP1 <br />
4 100 CAP2 <br />
4 101 CAP2 <br />
4 110 CAP3 <br />
4 111 CAP3 <br />
4 11:8 PRISEL 0000<br />
0000 CAP0.<br />
0001 CAP0.<br />
0010 0 .<br />
0011 1 .<br />
0100 CT16B0 PWM0 <br />
CT16B1 PWM1 <br />
www.xinnovatech.com 173
XN62Lxxx<br />
0101 CT16B0 CT16B1_MAT1 <br />
CT16B1 CT16B1_MAT0 <br />
0110 CT32B0_MAT0.<br />
0111 CT32B1_MAT0 <br />
1xxx<br />
<br />
15:12 SECSEL 0000<br />
0000 CAP0.<br />
0001 CAP1.<br />
0010 0 .<br />
0011 1 .<br />
0100 CT1B0 PWM0 <br />
CT1B1 PWM1 <br />
0101 CT1B0 CT16B1_MAT1 <br />
CT1B1 CT16B1_MAT0 <br />
0110 CT32B0_MAT0.<br />
0111 CT32B1_MAT0 <br />
1xxx<br />
<br />
16 IPS 0<br />
0 <br />
1 <br />
31: 17 - - . NA<br />
8.3.11.1 <br />
<br />
<br />
8.3.11.2 <br />
<br />
<br />
90° <br />
<br />
PHASE A<br />
(Primary)<br />
PHASE B<br />
(Secondary)<br />
COUNT<br />
+1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1<br />
Figure 8-2: <br />
174 www.xinnovatech.com
XN62Lxxx<br />
8.3.11.3 <br />
<br />
<br />
Primary<br />
Secondary<br />
COUNT 0 1 2 3 4<br />
5<br />
6 7 8<br />
Figure 8-3: <br />
8.3.11.4 <br />
<br />
Primary<br />
Secondary<br />
COUNT 0 1 2 3 4 3 2 1 0 1 2 3 4 5<br />
Figure 8-4: <br />
8.3.11.5 <br />
<br />
IPS<br />
Primary<br />
Secondary<br />
COUNT 0 1 2 3 4<br />
5<br />
6 7 8 9<br />
Figure 8-5: <br />
8.3.12 DMA<br />
0 /<br />
DMA <br />
DMA <br />
DMA <br />
DMA <br />
“1” <br />
DMA DMA <br />
DMA <br />
www.xinnovatech.com 175
XN62Lxxx<br />
9 32 /<br />
9.1 <br />
16 / XN62L <br />
32 / / <br />
SYSAHBCLKDIV <br />
<br />
SYSAHBCLKDIV /<br />
<br />
• <br />
32 /<br />
• /<br />
:<br />
– <br />
– <br />
– <br />
– <br />
– <br />
• 32 <br />
• 4 32 :<br />
– <br />
– <br />
– <br />
• :<br />
– <br />
– .<br />
– .<br />
• <br />
DMA .<br />
176 www.xinnovatech.com
XN62Lxxx<br />
CAPTURE REGISTER 3<br />
CAPTURE REGISTER 2<br />
CAPTURE GEGISTER 1<br />
CAPTURE REGISTER 0<br />
MATCH REGISTER 3<br />
MATCH REGISTER 2<br />
MATCH REGISTER 1<br />
MATCH REGISTER 0<br />
CAPTURE CONTROL REGISTER<br />
MATCH CONTROL REGISTER<br />
ENTERNAL MATCH REGISTER<br />
INTERRUPT REGISTER<br />
CONTROL<br />
=<br />
=<br />
LOAD[3:0]<br />
=<br />
=<br />
MAT[3:0]<br />
INTERRUPT<br />
CAP[3:0]<br />
TIMER CONTROL<br />
REGISTER<br />
Reset/Enable<br />
TIMER COUNTER<br />
+ -<br />
COUNT/<br />
Edge CNT<br />
QUAD<br />
CNT<br />
GATE<br />
CNT<br />
TRIGGER<br />
CNT<br />
SIGNED<br />
CNT<br />
PRI<br />
SEC<br />
SOURCE SEL<br />
MAXVAL<br />
PRESCALE REGISTER<br />
PRESCALE<br />
COUNTER<br />
CAP[3:0]<br />
C16B MAT<br />
Other C32B MAT<br />
PCLK<br />
Figure 9-1: 32 /<br />
<br />
9.2 <br />
Table 9-1: /<br />
<br />
CT32B0_CAP[3:0]<br />
CT32B1_CAP[3:0]<br />
CT32B0_MAT[3:0]<br />
CT32B1_MAT[3:0]<br />
<br />
<br />
:<br />
<br />
<br />
CT32B0/1 <br />
:<br />
CT32B0/1 <br />
(MR1:0) TC <br />
<br />
EMR PWMCON <br />
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XN62Lxxx<br />
9.3 <br />
32 / <br />
Table 9-2: 32 / <br />
(CT32B0 0x4001 8000; CT32B1 0x4001 C000)<br />
<br />
IR R/W 0x000 <br />
/<br />
.<br />
0<br />
TCR R/W 0x004 <br />
TCR <br />
0<br />
<br />
TC R/W 0x008 <br />
PCLK 1. TCR 0<br />
<br />
PR R/W 0x00C 32<br />
<br />
PC PR 0<br />
TC 1PC <br />
PC R/W 0x010 16<br />
<br />
PC PR 0<br />
TC 1PC <br />
MCR R/W 0x014 <br />
. MCR <br />
TC 0<br />
MR0 R/W 0x018 0. TC <br />
MR0 TC <br />
TC <br />
<br />
MR1 R/W 0x01C 1. MR0 . 0<br />
MR2 R/W 0x020 2. MR0 . 0<br />
MR3 R/W 0x024 3. MR0 . 0<br />
CCR R/W 0x028 <br />
CCR TC 0<br />
<br />
CR0 RO 0x02C <br />
0. CR0 CT32Bn_CAP0 <br />
TC 0<br />
CR1 RO 0x030 <br />
1. CR0 CT32Bn_CAP1 <br />
TC 0<br />
CR2 RO 0x034 <br />
2. CR0 CT32Bn_CAP2 <br />
TC 0<br />
CR3 RO 0x038 <br />
3. CR0 CT32Bn_CAP3 <br />
TC 0<br />
EMR R/W 0x03C <br />
. EMR <br />
0<br />
CT32Bn_MAT[3:0].<br />
- - 0x040 - 0x06C -<br />
CTCR R/W 0x070 . <br />
CTCR<br />
0<br />
0<br />
9.3.1 <br />
<br />
4 <br />
2 <br />
IR <br />
IR 1 <br />
0 <br />
DMA Table 9-3: (IR, 0x4001 8000 (CT32B0) 0x4001 C000(CT32B1)) <br />
<br />
0 MR0INT 0 0<br />
1 MR1INT 1 0<br />
178 www.xinnovatech.com
XN62Lxxx<br />
2 MR2INT 2 0<br />
3 MR3INT 3 0<br />
4 CR0INT 0 0<br />
5 CR1INT 1 0<br />
6 CR2INT 2 0<br />
7 CR3INT 3 0<br />
31:8 - - 0<br />
9.3.2 <br />
/<br />
.<br />
Table 9-4: <br />
(TCR, 0x4001 8004 (CT32B0) 0x4001 C004 (CT32B1)) <br />
<br />
0 CEN 0<br />
0 <br />
1 <br />
1 CRST 0<br />
0 .<br />
1 <br />
PCLK <br />
TCR <br />
31: 14 - - . N/A<br />
9.3.3 <br />
<br />
32 <br />
TC <br />
0xFFFF FFFF 0x0000 0000<br />
Table 9-5: <br />
(TC, 0x4001 8008 (CT32B0) 0x4001 5C008 (CT32B1)) <br />
<br />
31:0 TC 0<br />
9.3.4 <br />
32 <br />
Table 9-6: (PR, <br />
0x4001 800C (CT32B0) 0x4001 5C00C (CT32B1)) <br />
<br />
31:0 PCVAL . 0<br />
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XN62Lxxx<br />
9.3.5 <br />
32 <br />
PCLK <br />
<br />
PCLK <br />
PCLK TC PR = 0 <br />
PCLK <br />
PR = 1 2 PCLK .<br />
Table 9-7: <br />
(PC, 0x4001 8010 (CT32B0) 0x4001 5C010 (CT32B1)) <br />
<br />
31:0 PC 0<br />
9.3.6 <br />
<br />
Table 9-8: <br />
(MCR, <br />
0x4001 8014 (CT32B0) 0x4001 C014 (CT32B1)) <br />
<br />
0 MR0I MR0 TC 0<br />
1 <br />
0 <br />
1 MR0R MR0 TC TC <br />
0<br />
1 <br />
0 <br />
2 MR0S MR0 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
3 MR1I MR1 TC 0<br />
1 <br />
0 <br />
4 MR1R MR1 TC TC <br />
0<br />
1 <br />
0 <br />
5 MR1S MR1 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
6 MR2I MR2 TC 0<br />
1 <br />
0 <br />
7 MR2R MR2 TC TC <br />
0<br />
1 <br />
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XN62Lxxx<br />
0 <br />
8 MR2S MR2 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
9 MR3I MR3 TC 0<br />
1 <br />
0 <br />
10 MR3R MR3 TC TC <br />
0<br />
1 <br />
0 <br />
11 MR3S MR3 TC TC PC TCR CEN 0 0<br />
1 <br />
0 <br />
31:12 NA<br />
9.3.7 <br />
<br />
<br />
MCR Table 9-9: (MR0 ~ 3, 0x4001 8018 ~24 (CT32B0) ; 0x4001 C018 ~ 24 (CT32B1)) <br />
<br />
31:0 MATCH 0<br />
9.3.8 <br />
/<br />
<br />
“n” 0 1<br />
Table 9-10: <br />
(CCR, 0x4001 8028 (CT32B0) 0x4001 C028 (CT32B1)) <br />
<br />
0 CAP0RE 1 CT32Bn_CAP0 <br />
CT32Bn_CAP0 0 1 0<br />
1 <br />
0 <br />
CR0 TC <br />
1 CAP0FE 1 CT32Bn_CAP0 <br />
CT32Bn_CAP0 1 0 0<br />
1 <br />
0 <br />
CR0 TC <br />
2 CAP0I CT32Bn_CAP0 CT32Bn_CAP0<br />
<br />
CR0 0<br />
<br />
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XN62Lxxx<br />
1 <br />
0 <br />
3 CAP1RE CT32Bn_CAP1 <br />
CT32Bn_CAP1 0 1 0<br />
1 <br />
0 <br />
CR0 TC <br />
4 CAP1FE CT32Bn_CAP1 <br />
CT32Bn_CAP1 1 0 0<br />
1 <br />
0 <br />
CR0 TC <br />
5 CAP1I CT32Bn_CAP1 CT32Bn_CAP1<br />
<br />
CR0 0<br />
1 <br />
0 <br />
<br />
6 CAP2RE CT32Bn_CAP2 <br />
CT32Bn_CAP2 0 1 0<br />
1 <br />
0 <br />
CR0 TC <br />
7 CAP2FE CT32Bn_CAP2 <br />
CT32Bn_CAP2 1 0 0<br />
1 <br />
0 <br />
CR0 TC <br />
8 CAP2I CT32Bn_CAP2 CT32Bn_CAP2<br />
<br />
CR0 0<br />
1 <br />
0 <br />
<br />
9 CAP3RE CT32Bn_CAP3 <br />
CT32Bn_CAP3 0 1 0<br />
1 <br />
0 <br />
CR0 TC <br />
10 CAP3FE CT32Bn_CAP3 <br />
CT32Bn_CAP3 1 0 0<br />
1 <br />
0 <br />
CR0 TC <br />
11 CAP3I CT32Bn_CAP3 CT32Bn_CAP3<br />
<br />
CR0 0<br />
1 <br />
0 <br />
<br />
31:12 - - NA<br />
182 www.xinnovatech.com
XN62Lxxx<br />
9.3.9 <br />
<br />
<br />
Table 9-11: (CR0<br />
~ 3, 0x4001 802C ~38 (CT32B0) 0x4001 C02C~ 38 (CT32B1)) <br />
<br />
31:0 CAP 0<br />
9.3.10 <br />
<br />
CT32Bn_MAT[3:0] <br />
0 1 DMA <br />
Table 9-12: <br />
(EMR, 0x4001 803C (CT32B0) 0x4001 C03C (CT32B1)) <br />
<br />
0 EM0 0<br />
CT32B0_MAT0/CT32B1_MAT0 <br />
0<br />
<br />
TC MR0 <br />
<br />
EMR[5:4] IOCON 0=<br />
1= <br />
CT32B0_MAT0/CT32B1_MAT0 <br />
1 EM1 1<br />
CT32B1_MAT0/CT32B1_MAT1 <br />
0<br />
<br />
TC MR1 <br />
<br />
EMR[7:6] IOCON 0=<br />
1= <br />
CT32B0_MAT1/CT32B1_MAT1 <br />
2 EM2 2<br />
CT32B0_MAT2/CT32B1_MAT2 <br />
0<br />
<br />
TC MR2 <br />
<br />
EMR[9:8] IOCON 0=<br />
1= <br />
CT32B0_MAT2/CT32B1_MAT2 <br />
3 EM3 3<br />
CT32B0_MAT3/CT32B1_MAT3 <br />
0<br />
<br />
TC MR3 <br />
<br />
EMR[11:10] IOCON 0=<br />
1= <br />
CT32B0_MAT3/CT32B1_MAT3 <br />
5:4 EMC0 <br />
0<br />
0 00<br />
00 <br />
11 /<br />
<br />
CT32Bn_MAT0<br />
<br />
10 /<br />
1 <br />
CT32Bn_MAT0<br />
<br />
11 <br />
/ www.xinnovatech.com 183
XN62Lxxx<br />
7:6 EMC1 <br />
1<br />
1 00<br />
00 <br />
11 /<br />
<br />
CT32Bn_MAT1<br />
<br />
10 /<br />
1 <br />
CT32Bn_MAT1<br />
<br />
11 <br />
/ 9:8 EMC2 <br />
2<br />
2 00<br />
00 <br />
11 /<br />
<br />
CT32Bn_MAT2<br />
<br />
10 /<br />
1 <br />
CT32Bn_MAT2<br />
<br />
11 <br />
/ 11:10 EMC3 <br />
3<br />
3 00<br />
00 <br />
11 /<br />
<br />
CT32Bn_MAT3<br />
<br />
10 /<br />
1 <br />
CT32Bn_MAT3<br />
<br />
11 <br />
/ 31:12 - NA<br />
9.3.11 <br />
(CTCR)<br />
<br />
<br />
PCLK CTCR<br />
3:2 CAP <br />
CAP <br />
CAP <br />
CTCR 1:0 <br />
<br />
PCLK CAP <br />
CAP <br />
PCLK <br />
CAP /<br />
<br />
1/PCLK<br />
<br />
7:4 -<br />
- <br />
CAP <br />
<br />
<br />
Table 9-13: (CTCR, 0x4001 8070 (CT32B0) 0x4001 C070 (CT32B1)) <br />
<br />
184 www.xinnovatech.com
XN62Lxxx<br />
2:0 CTM / <br />
PCLK 00<br />
(PC) <br />
PC (TC)<br />
<br />
CTCR<br />
(CCR)<br />
2:0 000<br />
000 <br />
PCLK 001 TC<br />
11:8 CAP <br />
010 TC<br />
11:8 CAP <br />
011 TC<br />
11:8 CAP <br />
100 <br />
101 <br />
110 <br />
111 <br />
3 - - NA<br />
4 ENCC 1 7:5 - <br />
0<br />
7:5 SELCC 4 1 <br />
000<br />
4 <br />
000 CAP0 <br />
4 001 CAP0 <br />
4 010 CAP1 <br />
4 011 CAP1 <br />
4 100 CAP2 <br />
4 101 CAP2 <br />
4 110 CAP3 <br />
4 111 CAP3 <br />
4 11:8 PRISEL 0000<br />
0000 CAP0.<br />
0001 CAP1.<br />
0010 CAP2<br />
0011 CAP3.<br />
0100 CT32B0 PWM0 <br />
CT32B1 PWM1 <br />
0101 CT16b1_MAT0.<br />
0110 CT32b0_MAT0.<br />
0111 CT32b1_MAT0./ CT32b0_MAT0<br />
1xxx<br />
<br />
15:12 SECSEL 0000<br />
0000 CAP0.<br />
0001 CAP1.<br />
0010 CAP2<br />
0011 CAP3.<br />
www.xinnovatech.com 185
XN62Lxxx<br />
0100 CT32B0 PWM0 <br />
CT32B1 PWM1 <br />
0101 CT16b1_MAT0.<br />
0110 CT32b0_MAT0.<br />
0111 CT32b1_MAT0./ CT32b0_MAT0<br />
1xxx<br />
<br />
16 IPS 0<br />
0 <br />
1 <br />
31: 17 - - . NA<br />
9.3.12 DMA<br />
0 /<br />
<br />
DMA <br />
DMA <br />
DMA <br />
DMA <br />
“1” <br />
DMA DMA <br />
DMA <br />
186 www.xinnovatech.com
XN62Lxxx<br />
10 <br />
(WDT)<br />
10.1 <br />
<br />
<br />
• <br />
• <br />
• <br />
<br />
feed ok<br />
TC<br />
WDT_CLK<br />
24-bit down counter<br />
enable count<br />
FEED<br />
WD TV<br />
WINDOW<br />
feed sequence<br />
Detect and<br />
protection<br />
in<br />
range<br />
compare<br />
0<br />
WDINTVAL<br />
feed ok<br />
TC write<br />
feed error<br />
compare<br />
underflow<br />
compare<br />
shadow bit<br />
feed ok<br />
MOD<br />
register<br />
WDPRO TECT<br />
(MOD [4])<br />
WDTOF<br />
(MOD [2])<br />
WDINT<br />
(MOD [3])<br />
WDRESET<br />
(MOD [1])<br />
WDEN<br />
(MOD [0])<br />
chip reset<br />
watchdog<br />
interrupt<br />
Figure 10-1: <br />
www.xinnovatech.com 187
XN62Lxxx<br />
10.2 <br />
Table 10-1: (<br />
0x4000 4000)<br />
<br />
MOD R/W 0x000 <br />
<br />
0x0000 0003<br />
<br />
TC R/W 0x004 <br />
<br />
0x0000 FFFF<br />
FEED WO 0x008 <br />
0xAA<br />
NA<br />
0x55 TC<br />
TV RO 0x00C <br />
0xFF<br />
<br />
CLKSEL R/W 0x010 0<br />
WARNINT R/W 0x014 <br />
0<br />
WINDOW R/W 0x018 0xFF FFFF<br />
10.3 <br />
MOD WDEN RESET <br />
<br />
Table 10-2: <br />
(MOD - 0x4000 4000) <br />
<br />
0 WDEN <br />
WDLOCKEN <br />
WDEN 0<br />
0 <br />
1 <br />
1 WDRESET <br />
WDLOCKEN <br />
WDRESET 1<br />
0 <br />
1 <br />
2 WDTOF <br />
WDPROTECT=1 0 (<br />
WDTC <br />
0 )<br />
<br />
WDTOF 1<br />
<br />
3 WDINT <br />
WDWARNINT <br />
0<br />
<br />
1 4 WDPROTECT <br />
WDPROTECT <br />
0<br />
WDPROTECT <br />
0 (WDTC)<br />
188 www.xinnovatech.com
XN62Lxxx<br />
1 <br />
WARNINT WINDOW <br />
(WDTC) <br />
5 WDLOCKCLK <br />
0<br />
<br />
0 (WDCLK) <br />
1 <br />
PDRUNCFGPDSLEEPCFG PDAWAKECFG <br />
<br />
WDLOCKCLK <br />
/ IRC WDT <br />
WDLOCKCLK <br />
<br />
IRC <br />
<br />
WDLOCKCLK <br />
WDT <br />
PDSLEEPCFG <br />
WDLOCKCLK <br />
6 WDLOCKDP <br />
0<br />
<br />
0 <br />
1 PMU<br />
DPDEN 1<br />
7 WDLOCKEN <br />
0<br />
31: 8 <br />
<br />
0 WDEN WDRESET <br />
1 <br />
1 WDEN WDRESET <br />
WDLOCK <br />
WDEN <br />
<br />
• WDLOCKEN <br />
WDRESET 1<br />
<br />
• WDLOCKEN <br />
WDRESET 0<br />
<br />
Table 10-3: <br />
WDEN WDRESET <br />
0 X (0 or 1) <br />
1 0 <br />
<br />
WDWARNINT WDINT <br />
<br />
1 1<br />
<br />
<br />
WDWARNINT WDINT <br />
<br />
www.xinnovatech.com 189
XN62Lxxx<br />
10.3.1 <br />
TC <br />
TC <br />
0x00 FFFF 0xFF 0xFF TC<br />
TWDCLK × 256 × 4 MOD WDPROTECT 1<br />
<br />
WARNINT WINDOW <br />
TC <br />
WDTOF Table 10-4: <br />
(TC - 0x4000 4004) <br />
23:0 WDTC 0x00 FFFF<br />
31:24 - <br />
10.3.2 <br />
<br />
0xAA 0x55 WDTC <br />
WDTOF Table 10-5: <br />
(FEED - 0x4000 4008) <br />
<br />
7:0 WDFEED <br />
0xAA 0x55 -<br />
31:8 <br />
10.3.3 <br />
WDTV <br />
Table 10-6: <br />
(TV - 0x4000 400C) <br />
<br />
23:0 WDTV 0x00 00FF<br />
31:24 - NA<br />
10.3.4 <br />
<br />
31 IRC PDRUNCFG <br />
WDT <br />
Table 10-7: (CLKSEL<br />
- 0x4000 4010) <br />
<br />
1:0 WDSEL <br />
00<br />
<br />
WDLOCK WDSEL <br />
<br />
PDRUNCFG <br />
WDSEL 0x0<br />
IRC <br />
190 www.xinnovatech.com
XN62Lxxx<br />
0x1<br />
<br />
WDT <br />
<br />
0x2<br />
0x3<br />
.<br />
.<br />
30:2 - - . NA<br />
31 WDLOCK 0<br />
0 <br />
0<br />
1 <br />
WDLOCK <br />
10.3.5 <br />
WDWARNINT <br />
WDWARNINT WDCLK <br />
10 WARNINT 10 <br />
0 <br />
1,023 4,096<br />
WARNINT 0<br />
<br />
Table 10-8: <br />
(WARNINT - 0x4000 4014) <br />
<br />
9:0 WARNINT 0<br />
31:10 - NA<br />
10.3.6 <br />
WDWINDOW <br />
WDTV <br />
WDTV WDWINDOW <br />
<br />
WDWINDOW WDTV <br />
WDWINDOW 0x100<br />
Table 10-9: <br />
(WINDOW - 0x4000 4018) <br />
<br />
23:0 WDWINDOW <br />
.<br />
0xFF FFFF<br />
31:24 - NA<br />
10.4 <br />
<br />
PCLK WDCLKPCLK <br />
APB <br />
WDCLK <br />
wdt_clk <br />
wdt_clk IRC<br />
<br />
WDCLKSEL <br />
MODE www.xinnovatech.com 191
XN62Lxxx<br />
<br />
MOD TC APB <br />
WDCLK <br />
<br />
WDCLK <br />
WDCLK <br />
PCLK TV <br />
CPU <br />
<br />
PDRUNCFG <br />
MOD 5<br />
AHBCLKCTRL (PCLK)<br />
10.5 <br />
<br />
WDT <br />
<br />
• WDT / <br />
• <br />
• PDRUNCFGPDSLEEPCFGPDAWAKECFG <br />
WDT <br />
• WDT <br />
• <br />
<br />
• <br />
PDSLEEPCFGPDRUNCFG PDAWAKECFG WDT <br />
• <br />
WDT<br />
10.6 <br />
:<br />
WDCLK / 4<br />
Watchdog<br />
Counter<br />
125A 1259 1258 1257<br />
Early Feed<br />
Event<br />
Watchdog<br />
Reset<br />
Conditions:<br />
WINDOW = 0x1200<br />
WARNINT = 0x3FF<br />
TC = 0x2000<br />
Figure: 10-2 <br />
192 www.xinnovatech.com
XN62Lxxx<br />
WDCLK / 4<br />
Watchdog<br />
Counter<br />
125A 1259 1258 1257<br />
Early Feed<br />
Event<br />
Watchdog<br />
Reset<br />
Conditions:<br />
WINDOW = 0x1200<br />
WARNINT = 0x3FF<br />
TC = 0x2000<br />
Figure 10-3: <br />
WDCLK / 4<br />
Watchdog<br />
Counter<br />
0403 0402 0401 0400 03FF 03FE 03FD 03FC 03FB 03FA 03F9<br />
Watchdog<br />
Interrupt<br />
Conditions:<br />
WINDOW = 0x1200<br />
WARNINT = 0x3FF<br />
TC = 0x2000<br />
Figure 10-4: <br />
www.xinnovatech.com 193
XN62Lxxx<br />
11 xDSP<br />
11.1 <br />
XN62L <br />
DSP xDSP<br />
,<br />
xDSP ARM <br />
<br />
xDSP <br />
xDSP xDSP_PCLK <br />
<br />
SYSAHBCLKCTRL <br />
xDSP <br />
xDSP <br />
• CRC <br />
• 32 <br />
• Sine <br />
• Cosine <br />
• Arctangent <br />
• FIR<br />
IIR<br />
11.2 xDSP <br />
Table 11-1: <br />
( 0x5007 0000)<br />
<br />
CRC_MODE R/W 0x00 CRC 0x0000 0000<br />
CRC_SEED R/W 0x04 CRC 0x0000 FFFF<br />
CRC_SUM R/W 0x08 : CRC<br />
0x0000 FFFF<br />
: CRC <br />
~ ~ ~<br />
DIVIDEND R/W 0x100 32 0x0000 0000<br />
DIVISOR R/W 0x104 32 0x0000 0000<br />
QUOTIENT RO 0x108 32 0x0000 0000<br />
~ ~ ~<br />
CORDIC_CTRL R/W 0x200 CORDIC 0x0000 0000<br />
CORDIC_X R/W 0x204 32 CORDIC X 0x0000 0000<br />
CORDIC_Y R/W 0x208 32 CORDIC Y 0x0000 0000<br />
CORDIC_PH R/W 0x20C 32 CORDIC 0x0000 0000<br />
CORDIC_RLTX RO 0x210 32- CORDIC X 0x0000 0000<br />
CORDIC_RLTY RO 0x214 32- CORDIC Y 0x0000 0000<br />
CORDIC_RLTPH RO 0x218 32- CORDIC <br />
0x0000 0000<br />
~ ~ ~<br />
194 www.xinnovatech.com
XN62Lxxx<br />
FILTER_CR R/W 0x280 0x0000 0000<br />
FILTER_D R/W 0x284 0x0000 0000<br />
FILTER_START R/W 0x288 <br />
0x0000 0000<br />
FILTER_RESULT R/W 0x28C 0x0000 0000<br />
FILTER_C01<br />
R/W<br />
0x290<br />
0~15 0x0000 0000<br />
~<br />
~<br />
FILTER_CEF<br />
0x2AC<br />
11.2.1 CRC <br />
Table 11-2: CRC (CRC_MODE, 0x5007 0000) <br />
<br />
1:0 CRC_POLY CRC 00<br />
00 CRC-CCITT <br />
01 CRC-16 <br />
1X<br />
CRC-32 <br />
2 BIT_RVS_WR 0<br />
0 CRC_WR_DATA <br />
1 CRC_WR_DATA <br />
3 CMPL_WR 0<br />
0 CRC_WR_DATA 1 <br />
1 1 <br />
CRC_WR_DATA<br />
4 BIT_RVS_SUM CRC 0<br />
0 CRC_SUM <br />
1 CRC_SUM <br />
5 CMPL_SUM CRC 0<br />
0 CRC_SUM 1 <br />
1 1 <br />
CRC_SUM<br />
6 SEED_OP CRC 0<br />
0 <br />
1 <br />
CRC <br />
7 SEED_SET - 1 <br />
CRC 0<br />
31:8 - - NA<br />
11.2.2 CRC Seed <br />
Table 11-3: CRC (CRC_SEED, 0x5007 0004) <br />
<br />
31:0 CRC_SEED CRC 0x0000 FFFF<br />
11.2.3 CRC <br />
<br />
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XN62Lxxx<br />
Table 11-4: CRC (CRC_SUM, 0x5007 0008) <br />
<br />
31:0 CRC_SUM 1<br />
CRC<br />
0x0000 FFFF<br />
<br />
11.2.4 CRC <br />
<br />
CRC Table 11-5: CRC Data (CRC_DATA, 0x5007 0008) <br />
<br />
31:0 CRC_WR_DATA 1<br />
CRC<br />
-<br />
816 32 <br />
11.2.5 <br />
Table 11-6: (DIVIDEND, 0x5007 0100) <br />
<br />
31:0 DIVIDEND 32 . -<br />
11.2.6 <br />
Table 11-7: (DIVISOR, 0x5007 0104) <br />
<br />
31:0 DIVISOR 32 . -<br />
11.2.7 <br />
Table 11-8: <br />
(QUOTIENT, 0x5007 0108) <br />
<br />
31:0 QUOTIENT -<br />
11.2.8 CORDIC <br />
Table 11-9: CORDIC <br />
(CODIC_CTRL, 0x5007 0200) <br />
<br />
4:0 RES CORDIC 00<br />
0~14 <br />
15~31 16~32 CORDIC <br />
5 - . 0<br />
7:6 MODE CORDIC 00<br />
00 <br />
01 arctan CORDIC <br />
10 sin/cos CORDIC <br />
31:8 - - . 0<br />
196 www.xinnovatech.com
XN62Lxxx<br />
11.2.9 CORDIC X <br />
Table 11-10: CORDIC X (CODIC_X, 0x5007 0204) <br />
<br />
31:0 CORDIC_X 32 CORDIC X . - 2 RES-1 ~ 2 RES-1 . <br />
31~RES 0<br />
<br />
11.2.10 CORDIC Y <br />
Table 11-11: CORDIC Y (CODIC_Y, 0x5007 0208) <br />
<br />
31:0 CORDIC_Y 32 CORDIC Y . <br />
-2 RES-1 ~ 2 RES-1 . <br />
31~RES 0<br />
<br />
11.2.11 CORDIC Phase <br />
Table 11-12: CORDIC Phase (CODIC_PH, 0x5007 020C) <br />
<br />
31:0 CORDIC_PH 32 CORDIC Phase . <br />
-2 RES-1 ~ 2 RES-1 . <br />
31~RES0<br />
<br />
11.2.12 CORDIC X<br />
Table 11-13: CORDIC X (CODIC_RLTX, 0x5007 0210) <br />
<br />
31:0 CORDIC_RLTX <br />
0<br />
32 CORDIC X . -2 RES-1 ~ 2 RES-1 . <br />
31~RES<br />
11.2.13 CORDIC Y<br />
Table 11-14: CORDIC Y (CORDIC_RLTY, 0x5007 0214) <br />
<br />
31:0 CORDIC_RLTY <br />
0<br />
32 CORDIC Y . -2 RES-1 ~ 2 RES-1 . <br />
31~RES<br />
11.2.14 CORDIC Phase<br />
Table 11-15: CORDIC Phase (CORDIC_RLTPH, 0x5007 0218) <br />
<br />
31:0 CORDIC_RLTPH <br />
0<br />
32 CORDIC <br />
. <br />
-2 RES-1 ~ 2 RES-1 . <br />
31~RES<br />
11.2.15 <br />
Table 11-10: <br />
(FILTER_CR, 0x5007 0280) <br />
<br />
www.xinnovatech.com 197
XN62Lxxx<br />
15:0 SHF_DSRCSEL 0000<br />
0 D[n] <br />
D[n-1]<br />
1 D[n] <br />
19:16 FILTER_CYC .<br />
0<br />
0 1 <br />
~<br />
0xf 16 .<br />
FIR -<br />
1 IIR ,<br />
<br />
21:20 FILTER_MODE 00<br />
00 <br />
01 DMA <br />
DMA <br />
DMA<br />
10 DMA <br />
DMA <br />
DMA<br />
<br />
xDSP <br />
XDSP0_DMA_info <br />
.<br />
11 <br />
23:22 - - . 0<br />
24 FILTER_CLR 0<br />
0 .<br />
1 <br />
26:25 - - . 0<br />
31:27 OUTPUT_SHIFT .<br />
<br />
0<br />
FILTER_RESULT <br />
IIR <br />
11.2.16 <br />
Table 11-11: <br />
(FILTER_D, 0x5007 0284) <br />
<br />
15:0 FILTER_D <br />
. 0<br />
31:16 - 0<br />
11.2.17 <br />
Table 11-11: <br />
(FILTER_START, 0x5007 0288) <br />
<br />
0 FILTER_START <br />
1 0 0<br />
31:1 - 0<br />
11.2.18 <br />
Table 11-11: <br />
(FILTER_RESULT, 0x5007 028c) <br />
<br />
198 www.xinnovatech.com
XN62Lxxx<br />
15:0 FILTER_RESULT . 0<br />
16 FILTER_STAT <br />
1<br />
0 <br />
1 <br />
31:16 - 0<br />
11.2.19 <br />
Table 11-11: 0~7 (FILTER_C n, n=0~7, 0x5007 0290 ~ 0x5007 02ac) <br />
<br />
15:0 FILTER_C 2n 2n 0<br />
31:16 FILTER_C 2n+1 2n+1 0<br />
11.3 <br />
11.3.1 CRC <br />
CRC<br />
<br />
CRC-CCITT <br />
= x 16 + x 12 + x 5 + 1<br />
= 0xFFFF<br />
<br />
1<br />
CRC <br />
CRC 1 <br />
CRC_MODE = 0x0000 0000<br />
CRC_SEED = 0x0000 FFFF<br />
CRC-16 <br />
= x 16 + x 15 + x 2 + 1<br />
= 0x0000<br />
<br />
www.xinnovatech.com 199
XN62Lxxx<br />
1<br />
CRC <br />
CRC 1 <br />
CRC_MODE = 0x0000 0015<br />
CRC_SEED = 0x0000 0000<br />
CRC-32 <br />
32<br />
= + x 26 x+ x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1<br />
= 0xFFFF FFFF<br />
<br />
1<br />
CRC <br />
CRC 1 <br />
CRC_MODE = 0x0000 0036<br />
CRC_SEED = 0xFFFF FFFF<br />
11.3.2 32 <br />
xDSP 32 <br />
1. DIVIDENT .<br />
2. DIVISOR .<br />
3. QUOTIENT <br />
11.3.3 Sin/Cos/Arctan<br />
xDSP CORDIC (Coordinate Rotation Digital Computer) <br />
Sin, Cos Arctan. <br />
1. CORDIC xDSP CORDIC 32 <br />
CORDIC 16<br />
32 <br />
RES <br />
CORDIC_X, CORDIC_Y CORDIC_PH <br />
<br />
200 www.xinnovatech.com
XN62Lxxx<br />
2. <br />
CORDIC_X, CORDIC_Y CORDIC_PH <br />
Phase: -π/2 +π/2 CORDIC <br />
-π/2 +π/2 -0x64<br />
ED51 +0x6487 ED51 32 -0x6487 ED51 ( >> 16) +0x6487 (+0x6487 ED51 >> 16) 16 <br />
<br />
CORDIC x, y : ([RES:0]<br />
) -1 +1<br />
<br />
32 CORDIC -0x7FFF FFFF -1+0x7FFF FFFF<br />
+1<br />
3. CORDIC xDSP CORDIC Sin, Cos Arctan <br />
4. Sin :<br />
a) CORDIC_PH<br />
b) CORDIC 10Sin/Cos <br />
c) CORDIC_RLTY<br />
5. Cos :<br />
a) CORDIC_PH<br />
b) CORDIC 10Sin/Cos <br />
c) CORDIC_RLTX<br />
6. Arctan :<br />
a) CORDIC_X CORDIC_Y<br />
b) CORDIC 01Arctan <br />
c) CORDIC_RLTPH<br />
11.3.4 <br />
XN62L <br />
16 FIR<br />
5 IIR <br />
16 <br />
36 .<br />
www.xinnovatech.com 201
XN62Lxxx<br />
FILTER_D0<br />
D<br />
D<br />
D<br />
D<br />
D<br />
D<br />
C0<br />
C1<br />
C2<br />
C3<br />
<br />
Cn<br />
Cn+1<br />
Cn+2<br />
+ + + + + +<br />
Shift & clamp<br />
FILTER_RESULT<br />
Figure 11-1: n+2 FIR <br />
FILTER_D0<br />
D<br />
D<br />
D<br />
D<br />
D<br />
D<br />
D<br />
D<br />
D<br />
C0<br />
C1<br />
C2<br />
C3<br />
C4<br />
Cn<br />
Cn+1<br />
Cn+2<br />
Cn+1<br />
Cn+2<br />
+ + +<br />
+<br />
+ + +<br />
Shift &<br />
+ + FILTER_RESULT<br />
clamp<br />
Figure 11-2: 5 IIR <br />
Figure 11-1 Figure 11-2 D <br />
2 <br />
16 FIR <br />
32 <br />
FILTER_STAT <br />
xDSP <br />
FILTER_CR FILTER_MODE <br />
<br />
DMA DMA <br />
UART,<br />
TWS, ADC, SPI <br />
DMA_xDSP0 DMA <br />
DMA_xDSP1 DMA DMA<br />
<br />
5 IIR DMA <br />
Y=A0*X(n)+A1*X(n-1)+A2*X(n-2)+A3*X(n-3)+A4*X(n-4)+A5*X(n-5)-B1*Y(n-1)- B2*Y(n-2)- B3*Y(n-3)- B4*Y(n-4)- B5*Y(n-5):<br />
1. DMA_XDSP0_info DMA <br />
2. DMA_XDSP1_info DMA <br />
3. FILTER_CR: (1
XN62Lxxx<br />
5. <br />
www.xinnovatech.com 203
XN62Lxxx<br />
12 UART<br />
12.1 <br />
XN62L : UART1, UART2 UART0, UART3<br />
IrDA<br />
SYSAHBCLKCTRL <br />
UART <br />
( UART0CLKDIV /<br />
UART1CLKDIV / UART2CLKDIV / UART3CLKDIV)<br />
IRDAEN bit<br />
TX<br />
IrDA Transmit<br />
Encoder<br />
TXDn Pin<br />
UART<br />
IRDAEN bit<br />
RX<br />
IrDA Receiver<br />
Decoder<br />
RXDn Pin<br />
Figure 12-1: UART/IrDA <br />
Transmitter Buffer<br />
Shift Register<br />
TX<br />
TX FSM<br />
APB<br />
Interface<br />
Baud Rate Generator<br />
RX FSM<br />
Receiver Buffer<br />
Shift Register<br />
RX<br />
Figure 12-2: UART <br />
204 www.xinnovatech.com
XN62Lxxx<br />
12.2 <br />
Table 12-1: UART0,1, 2, 3 <br />
<br />
RXD0 UART0 <br />
TXD0 UART0 <br />
RXD1 UART1 <br />
TXD1 UART1 <br />
RXD2 UART2 <br />
TXD2 UART2 <br />
RXD3 UART3 <br />
TXD3 UART4 <br />
12.3 UART <br />
UART <br />
• UART0 0x4000 8000<br />
• UART1 0x4000 C000<br />
• UART2 0x4007 0000<br />
• UART3 0x4007 4000<br />
UART <br />
Table 12-2: <br />
(UART0: -0x4000 8000; UART1 - 0x4000 c000; UART2: -0x4007 0000; UART3 <br />
-0x4007 4000)<br />
<br />
RBR RO 0x000 <br />
NA<br />
THR WO 0x000 <br />
NA<br />
STATE R/W 0x004 RBR THR <br />
<br />
CTRL R/W 0x008 UART <br />
INTSTATUS R/W 0x00C UART <br />
0x00<br />
0x00<br />
0x0<br />
BAUDDIV R/W 0x010 UART 0x10<br />
12.3.1 <br />
RBR UART <br />
Table 12-3: UART <br />
(RBR) www.xinnovatech.com 205
XN62Lxxx<br />
<br />
7:0 RBR UART <br />
UART <br />
NA<br />
31:8 - -<br />
12.3.2 <br />
THR.<br />
Table 12-4: UART <br />
(THR) <br />
7:0 THR <br />
UART <br />
UART TX NA<br />
<br />
31:8 - -<br />
12.3.3 UART <br />
STATE <br />
UART <br />
Table 12-5: UART (STATE) <br />
<br />
1:0 - - . 00<br />
2 THROE 0<br />
1 <br />
1 <br />
3 RBROE 0<br />
1 <br />
1 <br />
4 BRADRDY <br />
0<br />
1 <br />
1 <br />
31:5 - - . NA<br />
12.3.4 UART <br />
CTRL UART <br />
Table 12-6: UART (CTRL3) <br />
<br />
0 THRE THR 0<br />
0 THR .<br />
1 THR <br />
1 RBRE RBR 0<br />
0 RBR .<br />
1 RBR.<br />
2 THRIE THR <br />
<br />
0<br />
0 THR .<br />
206 www.xinnovatech.com
XN62Lxxx<br />
1 THR .<br />
3 RBRIE RBR <br />
0<br />
0 RBR .<br />
1 RBR .<br />
4 THROIE THR 0<br />
0 THR <br />
.<br />
1 THR <br />
.<br />
5 RBROIE RBR 0<br />
0 RBR .<br />
1 RBR .<br />
6 THRHS THR <br />
0 0<br />
0 <br />
1 <br />
7 IRDAEN IrDA 0<br />
0 IrDA <br />
1 IrDA <br />
8 DMATXEN TX DMA 0<br />
0 <br />
1 <br />
9 DMARXEN RX DMA 0<br />
0 <br />
1 <br />
14:10 - - NA<br />
15 BRADEN 0<br />
0 <br />
1 <br />
31:10 - - NA<br />
12.3.5 UART <br />
INTSTATUS UART <br />
Table 12-7: UART <br />
(INTSTATUS) <br />
<br />
0 THRIES <br />
0<br />
0 <br />
1 <br />
1 <br />
1 RBRIES 0<br />
0 <br />
1 <br />
1 <br />
2 THROIES <br />
0<br />
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XN62Lxxx<br />
0 <br />
1 <br />
1 <br />
3 RBROIES <br />
0<br />
0 <br />
1 <br />
1 <br />
31:4 - - . NA<br />
STATE STATE<br />
<br />
<br />
12.3.6 UART<br />
UART <br />
(BAUDDIV) <br />
UART CLKDIV UART PCLK<br />
Table 12-8: UART <br />
(BAUDDIV) <br />
<br />
19:0 BAUDDIV <br />
16<br />
0x10<br />
31:20 - . 0<br />
<br />
UART baudrate=UARTn_PCLK / BAUDDIV<br />
UARTn_PCLK UART <br />
12.4 <br />
12.4.1 UART<br />
<br />
UART UART 1<br />
, , 8 1 , <br />
.<br />
<br />
<br />
BAUDDIV <br />
BAUDDIV UART <br />
CTRL BRADEN <br />
0x80<br />
UART <br />
UART<br />
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XN62Lxxx<br />
12.4.2 IrDA <br />
UART <br />
IRDAEN IrDA <br />
IrDA UART RXDn/TXDn <br />
3/16 /<br />
<br />
IrDA 1.63us <br />
UART IrDA <br />
<br />
TX<br />
Start Bit<br />
0<br />
Bit Period<br />
Stop Bit<br />
1 0 1 0 0<br />
1 1 0 1<br />
IrDA OUT<br />
IrDA IN<br />
3/16<br />
RX<br />
0<br />
1<br />
0 1 0 0 1 1 0 1<br />
Figure 12-3: UART IrDA <br />
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XN62Lxxx<br />
13 SPI<br />
13.1 <br />
XN62L SPI (Serial Peripheral interface)<br />
SPI 4 SSI (Synchronous Serial<br />
Interface )/<br />
4 16 SPI_PCLKsystem SYSAHBCLKDIV clock <br />
• SPI 4 SSI<br />
• <br />
• / <br />
• 8 FIFO<br />
First In First Out <br />
• 4<br />
-16-<br />
13.2 <br />
Table 13-1: SPI <br />
<br />
<br />
<br />
<br />
<br />
SPI SSI<br />
SCK I/O SCK CLK <br />
SCK/CLK <br />
SPI <br />
<br />
SPI <br />
SSEL I/O SSEL FS / <br />
SPI <br />
<br />
<br />
SPI <br />
<br />
<br />
<br />
MISO I/O MISO DR(M)<br />
DX(S)<br />
MISO<br />
<br />
SPI <br />
SPI <br />
SPI FS/SSEL <br />
MOSI I/O MOSI DX(M)<br />
DR(S)<br />
MOSI<br />
<br />
SPI <br />
SPI <br />
13.3 <br />
Table 13-2: <br />
( 0x4004 0000)<br />
210 www.xinnovatech.com
XN62Lxxx<br />
<br />
CR0 R/W 0x000 0<br />
0x0<br />
CR1 R/W 0x004 1 / <br />
DR R/W 0x008 <br />
FIFO<br />
0x0<br />
0x0<br />
SR RO 0x00C 0x0000 0003<br />
CPSR R/W 0x010 SPI 0x0<br />
IMSC R/W 0x014 <br />
0x0<br />
RIS RO 0x018 <br />
-<br />
MIS RO 0x01C 0x0000 0008<br />
ICR WO 0x020 <br />
NA<br />
DMACR R/W 0x024 DMA 0x0<br />
13.3.1 SPI <br />
0<br />
<br />
SPI .<br />
Table 13-3: SPI 0 (CR0 - 0x4004 0000) <br />
<br />
3:0 DSS <br />
0000<br />
0x0~0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
0x8<br />
0x9<br />
0xA<br />
0xB<br />
0xC<br />
0xD<br />
0xE<br />
0xF<br />
<br />
4-<br />
5-<br />
6-<br />
7-<br />
8-<br />
9-<br />
10-<br />
11-<br />
12-<br />
13-<br />
14-<br />
15-<br />
16-<br />
5:4 FRF 00<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
SPI<br />
SSI<br />
<br />
<br />
6 CPOL <br />
SPI 0<br />
0 SPI <br />
1 SPI <br />
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XN62Lxxx<br />
7 CPHA <br />
SPI 0<br />
31:8 - .<br />
0 SPI <br />
1 SPI <br />
13.3.2 SPI <br />
1<br />
<br />
SPI <br />
Table 13-4: SPI 1 (CR1 - 0x4004 0004) <br />
<br />
0 LBM <br />
0<br />
0 <br />
1 MISO<br />
MOSI<br />
1 SSE SPI 0<br />
0 SPI <br />
1 SPI <br />
SPI <br />
2 MS / SSE <br />
0<br />
0 SPI <br />
SCLKMOSI SSEL MISO <br />
1 SPI <br />
MISO SCLKMOSI SSEL <br />
3 SOD (MS 1 0<br />
= 1)<br />
SPI (MI<br />
SO)<br />
4 CSFL SPI SSEL 0<br />
0 SSEL <br />
1 SSEL <br />
SSE=1 5 RSFR FIFO 0<br />
0 FIFO<br />
1 FIFO<br />
6 FILTEN SPI 0<br />
0 <br />
1 <br />
31:7 NA<br />
13.3.3 SPI <br />
<br />
Table 13-5: SPI <br />
(DR - 0x4004 0008) <br />
<br />
212 www.xinnovatech.com
XN62Lxxx<br />
15:0 DATA <br />
TNF 1 Tx FIFO <br />
0x0000<br />
<br />
Tx FIFO <br />
SPI <br />
<br />
<br />
16 <br />
<br />
RNE 1 Rx FIFO <br />
<br />
SPI Rx FIFO <br />
16 <br />
0 31:16 - -<br />
13.3.4 SPI <br />
<br />
SPI <br />
Table 13-6: SPI (SR - 0x4004 000C) <br />
<br />
0 TFE FIFO <br />
FIFO <br />
1 0 1<br />
1 TNF FIFO Tx FIFO <br />
0 1 1<br />
2 RNE FIFO <br />
FIFO <br />
0 1 0<br />
3 RFF FIFO <br />
FIFO <br />
1 0 0<br />
4 BSY SPI <br />
0 /<br />
/ Tx FIFO <br />
<br />
1<br />
31:5 - NA<br />
0<br />
13.3.5 SPI <br />
<br />
SPI SPI <br />
SPI SPI_PCLK<br />
<br />
Table 13-7: SPI <br />
(CPSR - 0x4004 0010) <br />
<br />
7:0 CPSDVSR <br />
3 255 SPI_PCLK <br />
0 0<br />
0<br />
31:8 <br />
CR1 FILTEN CPSDVSR<br />
<br />
7<br />
: CPSR <br />
13.3.6 SPI<br />
<br />
<br />
SPI 4 <br />
Table 13-8: SPI <br />
(IMSC - 0x4004 0014) <br />
<br />
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XN62Lxxx<br />
0 RORIM <br />
Rx FIFO <br />
1 0<br />
<br />
1 RTIM <br />
1 Rx FIFO “<br />
0<br />
” <br />
SPI<br />
<br />
PCLK/(CPSDVSR × [SCR+1]) 32 <br />
2 RXIM Rx FIFO <br />
1 0<br />
3 TXIM Tx FIFO <br />
1 0<br />
31:4 - NA<br />
13.3.7 SPI <br />
IMSC <br />
1<br />
Table 13-9: SPI <br />
(RIS - 0x4004 0018) <br />
<br />
0 RORRIS Rx FIFO <br />
1 0<br />
1 RTRIS <br />
Rx FIFO “ ”<br />
0<br />
<br />
SPI <br />
PCLK/(CPSDVSR × [SCR+1]) 32 <br />
2 RXRIS Rx FIFO <br />
1 0<br />
3 TXRIS Tx FIFO <br />
1 1<br />
31:4 - NA<br />
13.3.8 SPI<br />
<br />
IMSC 1 SPI <br />
<br />
Table 13-10: SPI <br />
(MIS - 0x4004 001C) <br />
<br />
0 RORMIS Rx FIFO <br />
1 0<br />
1 RTMIS Rx FIFO “ ” <br />
1 0<br />
<br />
SPI PCLK/(CPSDVSR × [SCR+1]) 32 <br />
2 RXMIS Rx FIFO <br />
1 0<br />
3 TXMIS Tx FIFO <br />
1 0<br />
31:4 - NA<br />
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XN62Lxxx<br />
13.3.9 SPI <br />
<br />
1 SPI FIFO / <br />
FIFO IMSC <br />
Table 13-11: SPI <br />
(ICR - 0x4004 0020) <br />
<br />
0 RORIC 1 Rx FIFO <br />
NA<br />
1 RTIC 1 Rx FIFO <br />
NA<br />
<br />
SPI <br />
PCLK/(CPSDVSR × [SCR+1]) 32 <br />
31:2 - NA<br />
13.3.10 SPI DMA <br />
DMACR DMA /<br />
Table 13-12: SPI DMA <br />
(DMACR - 0x4004 0024) <br />
<br />
0 RXDMAE DMA 0<br />
0 DMA <br />
1 FIFO DMA <br />
1 TXDMAE DMA 0<br />
0 DMA <br />
1 FIFO DMA <br />
31:2 NA<br />
13.4 <br />
13.4.1 SPI <br />
SPI 4 <br />
SSEL SPI<br />
<br />
SCK <br />
SPICR0 <br />
CPOL CPHA <br />
(CPOL) (CPHA)<br />
<br />
CPOL <br />
0 SCK <br />
CPOL 1<br />
CLK <br />
CPHA <br />
CPHA 0 <br />
CPHA <br />
1 <br />
CPOL=0, CPHA=0 SPI<br />
CPOL = 0 CPHA = 0 SPI <br />
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XN62Lxxx<br />
CLK<br />
SSEL<br />
MOSI<br />
MSB<br />
LSB<br />
MISO<br />
MSB<br />
LSB<br />
Q<br />
4 to 16 bit<br />
a. Single transfer with CPOL = 0 and CPHA = 0<br />
MSB<br />
LSB<br />
MSB<br />
LSB<br />
MSB<br />
LSB<br />
Q<br />
MSB<br />
LSB<br />
Q<br />
4 to 16 bit<br />
4 to16 bit<br />
Figure 13-1: CPOL=0 CPHA=0 SPI a) b) <br />
<br />
• CLK <br />
• SSEL<br />
CSFL=0<br />
• MOSI/MISO <br />
SPI FIFO <br />
SSEL <br />
<br />
MISO <br />
MOSI1/2 SCK <br />
MOSI <br />
1/2 SCK SCK <br />
SCK <br />
SCK <br />
SCK<br />
SSEL <br />
CSFL=0 CSFL=1 SSEL <br />
CPOL=0, CPHA=1 SPI<br />
CPOL = 0 CPHA = 1 SPI <br />
CLK<br />
SSEL<br />
MOSI<br />
MSB<br />
LSB<br />
MISO<br />
Q<br />
MSB<br />
LSB<br />
Q<br />
4 to 16 bit<br />
216 www.xinnovatech.com
XN62Lxxx<br />
Figure 13-2: SPI CPOL = 0 CPHA = 1 <br />
<br />
• CLK <br />
• SSELCSFL=0<br />
• MOSI/MISO <br />
SPI FIFO <br />
SSEL <br />
MOSI<br />
1/2 SCK <br />
SCK SCK <br />
SCK <br />
<br />
SCK SSEL <br />
CSFL=0 CSFL=1 SSEL <br />
CPOL = 1, CPHA = 0 SPI<br />
CPOL=1 CPHA=0 SPI <br />
CLK<br />
SSEL<br />
MOSI<br />
MSB<br />
LSB<br />
MISO<br />
MSB<br />
LSB<br />
Q<br />
4 to 16 bit<br />
a. Single transfer with CPOL = 1 and CPHA = 0<br />
MSB<br />
LSB<br />
MSB<br />
LSB<br />
MSB LSB Q<br />
MSB LSB Q<br />
4 to 16 bit<br />
4 to 16 bit<br />
b. Continuous transfer with CPOL = 1 and CPHA = 0<br />
Figure 13-3: SPI CPOL = 1 CPHA = 0 (a) (b) <br />
<br />
• CLK <br />
• SSELCSFL=0<br />
• MOSI/MISO <br />
www.xinnovatech.com 217
XN62Lxxx<br />
SPI FIFO <br />
SSEL <br />
<br />
MISO <br />
MOSI 1/2 SCK <br />
MOSI <br />
1/2 SCK SCK <br />
SCK <br />
SCK <br />
SCK SSEL <br />
CSFL=0 CSFL=1 SSEL <br />
CPOL = 1, CPHA = 1 SPI<br />
CPOL = 1 CPHA = 1 SPI <br />
CLK<br />
SSEL<br />
MOSI<br />
MSB<br />
LSB<br />
MISO<br />
Q<br />
MSB<br />
LSB<br />
Q<br />
4 to 16 bit<br />
Figure 13-4: SPI CPOL = 1 CPHA = 1 <br />
<br />
• CLK <br />
• SSELCSFL=0<br />
• MOSI/MISO <br />
SPI FIFO <br />
SSEL <br />
MOSI<br />
1/2 SCK <br />
SCK SCK<br />
<br />
SCK <br />
SCK SSEL <br />
CSFL=0 CSFL=1 SSEL <br />
13.4.2 SSI <br />
SPI<br />
4 <br />
218 www.xinnovatech.com
XN62Lxxx<br />
CLK<br />
FS<br />
DX/DR<br />
MSB<br />
LSB<br />
4 to 16 bit<br />
a. Single frame transfer<br />
CLK<br />
FS<br />
DX/DR<br />
MSB LSB MSB LSB<br />
4 to 16 bit<br />
4 to 16 bit<br />
b. Continuous/back-to-back frames transfer<br />
Figure 13-5:4a)<br />
b) / 2 <br />
<br />
CLK FS <br />
SPI DX <br />
FIFO <br />
FS <br />
CLK <br />
FIFO <br />
CLK 4 16 MSB DX <br />
MSB <br />
DR <br />
CLK SPI <br />
CLK <br />
FIFO<br />
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XN62Lxxx<br />
14 Flash QSPI<br />
14.1 <br />
XN62L Flash QSPI<br />
I/ODUAL I/OQUAD Flash <br />
SPI (Serial<br />
Peripheral interface)/<br />
Flash QSPI<br />
_PCLKsystem cloc<br />
<br />
SYSAHBCLKDIV <br />
• / / Flash<br />
• <br />
• 16FIFO<br />
First In First Out<br />
• SPI 00,0 3 1,1<br />
14.2 <br />
Table 14-1: Flash <br />
<br />
<br />
QSPI_CLK I/O <br />
CLK <br />
QSPI_CS I/O Flash <br />
C<br />
LK <br />
<br />
QSPI_DI(IO 0) I/O Flash ( /<br />
0) (1)<br />
QSPI_DO(IO 1) I/O Flash ( /<br />
1) (1)<br />
QSPI_WP(IO 2) I/O Flash ( /<br />
2) (2)<br />
QSPI_HOLD(IO 3) I/O Flash ( /<br />
(1). IO 0 IO 1 I/O<br />
<br />
(2). IO 0-IO 3 I/O <br />
3) (2)<br />
14.3 <br />
Table 14-2: ( 0x4007 8000)<br />
<br />
CR0 R/W 0x000 0 0x08<br />
CR1 R/W 0x004 1 / <br />
DR R/W 0x008 <br />
FIFO<br />
0x0<br />
NA<br />
SR RO 0x00C 0x03<br />
CPSR R/W 0x010 0x0<br />
220 www.xinnovatech.com
XN62Lxxx<br />
IMSC R/W 0x014 <br />
RIS RO 0x018 <br />
0x0<br />
0x05<br />
MIS RO 0x01C 0x0<br />
ICR WO 0x020 0x0<br />
DMACR R/W 0x024 DMA 0x0<br />
14.3.1 Flash<br />
0<br />
.<br />
Table 14-3: Flash <br />
0 (CR0 - 0x4007 8000) <br />
<br />
0 ENABLE 0 1 Flash 0<br />
1 RE <br />
DUAL QUAD <br />
/<br />
0<br />
<br />
2 TE <br />
DUAL QUAD <br />
/<br />
0<br />
<br />
3 CSS CS 1<br />
4 CPOL 0<br />
0 <br />
CLK <br />
1 <br />
CLK <br />
5 CPHA 0<br />
0 <br />
1 <br />
7:6 MODE Flash 00<br />
00 <br />
01 DUAL <br />
10 QUAD <br />
11 <br />
15:8 RNUM <br />
0<br />
RNUM=0 1 <br />
RNUM=255 256 <br />
14.3.2 Flash<br />
1<br />
<br />
Flash <br />
Table 14-4: Flash <br />
1 (CR1 - 0x4007 8004) <br />
<br />
0 RFIFOCLR FIFO 1 FIFO 0 0<br />
1 TFIFOCLR FIFO 1 FIFO 0 0<br />
2 WP Flash WP <br />
QUAD WP <br />
IO 2WP 0<br />
<br />
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XN62Lxxx<br />
3 HOLD Flash Hold <br />
QUAD HOLD <br />
IO 3 HOLD 0<br />
<br />
31:4 - - NA<br />
14.3.3 Flash<br />
<br />
Table 14-5: Flash <br />
(DR - 0x4007 8008) <br />
<br />
7:0 DATA <br />
TNF 1 Tx FIFO <br />
NA<br />
<br />
Tx FIFO <br />
QSPI <br />
<br />
<br />
RNE 1 Rx FIFO <br />
<br />
QSPI Rx FIFO <br />
31:8 - NA<br />
14.3.4 Flash<br />
<br />
Flash <br />
Table 14-6: Flash <br />
(SR - 0x4007 800C) <br />
<br />
0 TFE FIFO <br />
FIFO <br />
1 0 1<br />
1 TNF FIFO Tx FIFO <br />
0 1 1<br />
2 RNE FIFO <br />
FIFO <br />
0 1 0<br />
3 RFF FIFO <br />
FIFO <br />
1 0 0<br />
4 BSY <br />
Flash <br />
0 /<br />
/ 0<br />
Tx FIFO <br />
1<br />
31:5 - NA<br />
14.3.5 Flash<br />
<br />
Flash QSPI<br />
_PCLK <br />
Table 14-7:<br />
(CPSR - 0x4007 8010) <br />
<br />
7:0 CPSDVSR <br />
1 255 QSPI_PCLK <br />
0 0<br />
31:8 <br />
QSPI _PCLK<br />
: CPSR <br />
222 www.xinnovatech.com
XN62Lxxx<br />
14.3.6 <br />
<br />
<br />
4 Table 14-8:<br />
(IMSC - 0x4007 8014) <br />
<br />
0 TXEND Tx FIFO <br />
1 0<br />
1 RXIM Rx FIFO <br />
1 0<br />
2 TXIM Tx FIFO <br />
1 0<br />
3 RXEND <br />
RNUM <br />
1 0<br />
31:4 - NA<br />
14.3.7 <br />
IMSC <br />
1<br />
Table 14-9:<br />
(RIS - 0x4007 8018) <br />
<br />
0 TXERIS Tx FIFO <br />
1 1<br />
1 RXRIS Rx FIFO <br />
1 0<br />
2 TXRIS Tx FIFO <br />
1 1<br />
3 RXERIS <br />
RNUM <br />
1 0<br />
31:4 - NA<br />
14.3.8 <br />
<br />
IMSC 1<br />
<br />
Table 14-10:<br />
(MIS - 0x4007 801C) <br />
<br />
0 TXEMIS Tx FIFO <br />
1 0<br />
1 RXMIS Rx FIFO <br />
1 0<br />
2 TXMIS Tx FIFO <br />
1 0<br />
3 RXEMIS <br />
RNUM <br />
1 0<br />
31:4 - NA<br />
14.3.9 <br />
<br />
1 <br />
Table 14-11:<br />
(ICR - 0x4007 8020) <br />
<br />
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XN62Lxxx<br />
0 RXERIC 1 FIFO <br />
(MIS) RXEMIS flash <br />
FIFONA<br />
31:1 - NA<br />
14.3.10 DMA <br />
DMACR DMA /<br />
Table 14-12: DMA <br />
(DMACR - 0x4007 8024) <br />
<br />
0 RXDMAE DMA 0<br />
0 DMA <br />
1 FIFO DMA <br />
1 TXDMAE DMA 0<br />
0 DMA <br />
1 FIFO DMA <br />
31:2 NA<br />
14.4 <br />
14.4.1 <br />
<br />
SPI 00,0 31,1<br />
SPICR0 <br />
CPOL CPHA <br />
CPOL=0, CPHA=0<br />
CPOL = 0 CPHA = 0 <br />
CLK<br />
CS<br />
DI<br />
MSB<br />
LSB<br />
DO<br />
MSB<br />
LSB<br />
Q<br />
8 bit<br />
<br />
• CLK <br />
• DI/DO <br />
CPOL = 1, CPHA = 1 SPI<br />
Figure 14-1: CPOL=0 CPHA=0 <br />
CPOL = 1 CPHA = 1 SPI <br />
224 www.xinnovatech.com
XN62Lxxx<br />
CLK<br />
CS<br />
DI<br />
MSB<br />
LSB<br />
DO<br />
Q<br />
MSB<br />
LSB<br />
Q<br />
8 bit<br />
Figure 14-2: CPOL = 1 CPHA = 1 <br />
<br />
• CLK <br />
• DI/DO <br />
14.4.2 DUAL <br />
<br />
Flash <br />
DUAL /<br />
IO 0 IO 1<br />
DUAL Flash <br />
Begin with Standard Mode<br />
CLK<br />
CS<br />
DI(IO0)<br />
MSB<br />
LSB<br />
MSB<br />
LSB<br />
DO(IO1)<br />
High Impedance<br />
8 bit<br />
address<br />
Change to DUAL mode<br />
CLK<br />
CS<br />
DI(IO0)<br />
6 4 2 0<br />
6 4 2 0<br />
DO(IO1)<br />
7 5 3 1<br />
7 5 3 1<br />
dummy<br />
Figure 14-3:DUAL Flash<br />
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XN62Lxxx<br />
14.4.3 QUAD <br />
QUAD /<br />
IO 0IO 1IO 2IO 3 QUAD Flash <br />
Begin with Standard Mode<br />
CLK<br />
CS<br />
DI(IO0)<br />
MSB<br />
LSB<br />
MSB<br />
LSB<br />
DO(IO1)<br />
High Impedance<br />
WP(IO2)<br />
HOLD(IO3)<br />
8 bit<br />
address<br />
Change to QUAD mode<br />
CLK<br />
CS<br />
DI(IO0)<br />
<br />
<br />
<br />
<br />
<br />
DO(IO1)<br />
<br />
<br />
<br />
<br />
<br />
WP(IO2)<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
HOLD(IO3)<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
dummy<br />
byte0 byte1 byte2 byte3<br />
igure 14-4: QUAD Flash<br />
F<br />
226 www.xinnovatech.com
XN62Lxxx<br />
www.xinnovatech.com 227
XN62Lxxx<br />
15 TWS<br />
15.1 <br />
TWS <br />
I 2 C <br />
I 2 C • I<br />
2<br />
C<br />
• TWS<br />
• <br />
• <br />
• 3MHz<br />
• 4<br />
<br />
• TWS <br />
pull-up<br />
resistor<br />
pull-up<br />
resistor<br />
SDA<br />
Compatible I 2 C bus<br />
SCL<br />
SDA SCL<br />
XN62L<br />
OTHER XN62L<br />
OTHER I 2 C<br />
Compatible<br />
DEVICE<br />
Figure 15-1: TWS <br />
15.2 <br />
Table 15-1: TWS <br />
<br />
SDA<br />
SCL<br />
/ <br />
/ <br />
TWS <br />
TWS <br />
228 www.xinnovatech.com
XN62Lxxx<br />
15.3 <br />
Table 15-2: <br />
( 0x4000 0000)<br />
<br />
<br />
CONSET R/W 0x000 TWS <br />
1 TWS <br />
0x00<br />
0 <br />
STAT RO 0x004 TWS <br />
TWS <br />
0x1F<br />
<br />
DAT R/W 0x008 TWS <br />
. / <br />
/ 0x00<br />
<br />
ADR0 R/W 0x00C TWS <br />
0 7 <br />
TWS 0x00<br />
<br />
.<br />
SCLH R/W 0x010 <br />
TWS <br />
SCLL R/W 0x014 <br />
TWS <br />
0x04<br />
0x04<br />
CONCLR WO 0x018 TWS <br />
1 TWS <br />
NA<br />
0 TWS <br />
- - 0x01C 0x00<br />
ADR1 R/W 0x020 TWS <br />
1 7 <br />
TWS 0x00<br />
<br />
ADR2 R/W 0x024 TWS <br />
2 7 <br />
TWS 0x00<br />
<br />
ADR3 R/W 0x028 TWS <br />
3 7 <br />
TWS 0x00<br />
<br />
DATA_<br />
BUFFER<br />
RO 0x02C <br />
. <br />
9 8 ACK NACK DAT 0x00<br />
<br />
8 <br />
DATA_BUFFER<br />
MASK0 R/W 0x030 TWS <br />
0<br />
ADR0 0x00<br />
MASK1 R/W 0x034 TWS <br />
1<br />
ADR0 0x00<br />
MASK2 R/W 0x038 TWS <br />
2<br />
ADR0 0x00<br />
MASK3 R/W 0x03C TWS <br />
3<br />
ADR0 0x00<br />
15.3.1 TWS<br />
CONSET TWS <br />
1 TWS <br />
0 Table 15-3: TWS <br />
(CONSET - 0x4000 0000) <br />
<br />
0 TXRX / <br />
1 MASL / <br />
0x0<br />
0x0<br />
2 AA 0x0<br />
3 SI TWS <br />
0x0<br />
www.xinnovatech.com 229
XN62Lxxx<br />
4 STO 0x0<br />
5 STA 0x0<br />
6 TWSEN TWS 0x0<br />
31:7 - 0x0<br />
TXRX: / <br />
• TXRX 1 , TWS<br />
• TXRX 0 , TWS<br />
MASL: / <br />
• MASL 1 , TWS<br />
• MASL 0 , TWS<br />
AA: <br />
• AA 1 SCL <br />
1. <br />
2. TWS<br />
3. TWS<br />
• CONCLR AAC 1 AA AA 0 SCL <br />
SDA<br />
1. TWS<br />
2. TWS<br />
SI: <br />
• TWSSI<br />
SCL <br />
SI<br />
SI<br />
CONCLR<br />
SI C1 <br />
STO: <br />
• TWS<br />
<br />
TWS <br />
STO ST<br />
<br />
”<br />
STO <br />
STA: <br />
• <br />
TWS <br />
1 TWS <br />
<br />
<br />
STA TWS<br />
CONCLR<br />
STAC 1<br />
STASTA 0 <br />
<br />
STA STO TWS<br />
TWS<br />
<br />
230 www.xinnovatech.com
XN62Lxxx<br />
TWSEN: TWS <br />
• TWS EN 1 TWSCONCLR<br />
TWS<br />
ENC 1 TWSEN TWSEN<br />
0 TWS<br />
• TWSEN 0 SDA SCL TWS<br />
“ ” STO<br />
0 TWSEN <br />
TWS<br />
TWS<br />
EN TWS AA<br />
15.3.2 TWS <br />
TWS <br />
TWS TWS<br />
<br />
Table 15-4: TWS <br />
(STAT - 0x4000 0004) <br />
<br />
6:0 STATUS TWS <br />
Table 15-14~Table 15-17.<br />
0x1F<br />
8 SLVADDMATCH <br />
1 0<br />
9 SLVRXBUFFULL (<br />
: 0x08) 0<br />
10 SLVTXBUFEMPTY (<br />
: 0x08) 0<br />
31: 11 - NA<br />
15.3.3 TWS <br />
<br />
SI <br />
CPU SI DAT <br />
DAT <br />
MSB 7<br />
<br />
DAT MSB Table 15-5: TWS <br />
(DAT - 0x4000 0008) <br />
<br />
7:0 DATA 0<br />
31: 8 - -<br />
15.3.4 TWS <br />
0~3<br />
4 /<br />
TWS <br />
Table 15-6: TWS 0 (ADR0- 0x4000 000CADR1 - 0x4000 0020, ADR2 - 0x4000 0024, ADR3 -0x4000 0028)) <br />
<br />
0 0<br />
7:1 ADDR TWS <br />
0x00<br />
31: 8 - -<br />
15.3.5 TWS <br />
Table 15-7: TWS <br />
(SCLH - 0x4000 0010) <br />
<br />
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XN62Lxxx<br />
15:0 SCLH SCL 0x0004<br />
31: 16 - -<br />
15.3.6 TWS <br />
Table 15-8: TWS <br />
(SCLL - 0x4000 0014) <br />
<br />
15:0 SCLL SCL 0x0004<br />
31: 16 - -<br />
:<br />
<br />
SCLH SCLL <br />
SCLH SCL TWS_PCLK <br />
SCLL<br />
SCL TWS_PCLK TWS_PCLK<br />
APB TWS = TWS_PCLK/(SCLH + SCLL)<br />
15.3.7 TWS<br />
CONCLR <br />
CON <br />
TWS <br />
1 TWS <br />
0 Table 15-9: TWS <br />
(CONCLR - 0x4000 0018) <br />
<br />
0 TXRX / <br />
1 TWSONSET TXRX 0 . NA<br />
1 MASL / <br />
1 TWSONSET MASL 0 . 0<br />
2 AAC <br />
1 TWSONSET AA 0 0<br />
3 SIC <br />
1 TWSONSET SI 0 0<br />
4 - . NA<br />
5 STAC <br />
1 TWSONSET STA 0 0<br />
6 TWSENC TWS <br />
1 TWSONSET TWSEN 0 0<br />
31: 7 - -<br />
15.3.8 TWS <br />
Table 15-10: TWS <br />
(DATA_BUFFER - 0x4000 002C) <br />
<br />
7:0 DATA <br />
DAT <br />
8 0<br />
31: 8 - -<br />
15.3.9 TWS <br />
0~3<br />
4 <br />
7 7:1 <br />
ADRn <br />
<br />
ADRn <br />
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XN62Lxxx<br />
Table 15-11: TWS <br />
(MASK0 - 0x4000 0030, MASK1 - 0x4000 0034,MASK2 - 0x4000 0038, MASK3 - 0x4000 003C) <br />
<br />
0 - . 0<br />
7:1 MASK 0x00<br />
31: 8 - . 0<br />
15.4 TWS<br />
I 2 C <br />
TWS <br />
TWS 4 <br />
<br />
TWS <br />
15.4.1 <br />
<br />
CONSET MASL 1 <br />
TXRX<br />
1 <br />
TWSEN 1 TWS AA 0<br />
I2C <br />
STASTO SI 0 CONCLR SIC 1 <br />
SI <br />
STA STA, STO SI 0SI 1 CONCLR SIC <br />
<br />
STA Table 15-12: TWS CONSET <br />
7 6 5 4 3 2 1 0<br />
- TWSEN STA STO SI AA MASL TXRX<br />
- 1 0 0 0 0 1 1<br />
<br />
7 <br />
0<br />
<br />
<br />
8 <br />
<br />
STA TWS <br />
TWS <br />
SI STAT <br />
0x01<br />
<br />
DAT <br />
SI CONCLR SIC 1 SI<br />
<br />
R/W SI<br />
<br />
0x0b, 0x4b 0x14<br />
Table 15-14 Table 15-17<br />
S SLAVE ADDRESS RW=0 A DATA A DATA A/A# P<br />
n bytes data transmitted<br />
from Master to Slave<br />
from Slave to Master<br />
A = Acknowledge (SDA low)<br />
A# = Not acknowledge (SDA high)<br />
S = START condition<br />
P = STOP condition<br />
Figure 15-2:<br />
www.xinnovatech.com 233
XN62Lxxx<br />
successful<br />
transmission<br />
to a Slave<br />
Receiver<br />
S<br />
SLA W A DATA A P<br />
01H<br />
0BH<br />
14H<br />
next transfer<br />
started with a<br />
Repeated Start<br />
condition<br />
S<br />
SLA<br />
W<br />
Not<br />
Acknowledge<br />
received after<br />
the Slave<br />
address<br />
A# P R<br />
01H<br />
4BH<br />
Not<br />
Acknowledge<br />
received after a<br />
Data byte<br />
A# P<br />
54H<br />
to Master<br />
receive<br />
mode,<br />
entry<br />
= MR<br />
from Master to Slave<br />
from Slave to Master<br />
DATA<br />
A<br />
any number of data bytes and their associated Acknowledge bits<br />
n<br />
This number (contained in STAT) corresponds to a defined state of the TWS bus<br />
Figure 15-3:<br />
15.4.2 <br />
<br />
(SLA+R)<br />
DAT<br />
CON SI <br />
(SI)<br />
STAT <br />
0x0b, 0x4b, 0x1d.(AA 0x680x78 = 1) 0xB0 Table 15-15 <br />
TWS <br />
SI AA <br />
TWS <br />
<br />
SI <br />
AA <br />
TWS “ ”<br />
<br />
”<br />
SI STO STA<br />
SI <br />
234 www.xinnovatech.com
XN62Lxxx<br />
S SLAVE ADDRESS RW=1 A DATA A DATA A# P<br />
n bytes data received<br />
from Master to Slave<br />
from Slave to Master<br />
A = Acknowledge (SDA low)<br />
A# = Not acknowledge (SDA high)<br />
S = START condition<br />
P = STOP condition<br />
Figure 15-4: <br />
MR<br />
successful<br />
transmission<br />
to a Slave<br />
transmitter<br />
S<br />
SLA R A DATA DATA A# P<br />
01H<br />
0BH<br />
1DH<br />
1DH<br />
next transfer<br />
started with a<br />
Repeated Start<br />
condition<br />
S<br />
SLA<br />
R<br />
Not<br />
Acknowledge<br />
received after<br />
the Slave<br />
address<br />
A# P W<br />
21H<br />
22H<br />
4BH<br />
to Master<br />
transmit<br />
mode,<br />
entry<br />
= MT<br />
from Master to Slave<br />
from Slave to Master<br />
DATA<br />
A<br />
any number of data bytes and their associated Acknowledge bits<br />
n<br />
this number (contained in STAT) corresponds to a defined state of the TWS bus<br />
Figure 15-5: <br />
15.4.3 <br />
<br />
-3) (MASK0<br />
-3) <br />
TWS (CONSET)<br />
Table 15-13: TWS CONSET <br />
<br />
www.xinnovatech.com 235
XN62Lxxx<br />
7 6 5 4 3 2 1 0<br />
- TWSEN STA STO SI AA MASL TXRX<br />
- 1 0 0 0 1 0 0<br />
MASL 0 TWSEN <br />
TWS AA 1 STA<br />
STO SI 0 ADR CONSET TWS <br />
0(W)<br />
<br />
1(R)SI<br />
(STAT)<br />
<br />
Table 15-16 S SLAVE ADDRESS RW=0 A DATA A DATA A/A# P/Sr<br />
n bytes data received<br />
from Master to Slave<br />
from Slave to Master<br />
A = Acknowledge (SDA low)<br />
A# = Not acknowledge (SDA high)<br />
S = START condition<br />
P = STOP condition<br />
Sr = Repeated START condition<br />
Figure 15-6: <br />
236 www.xinnovatech.com
XN62Lxxx<br />
reception of the<br />
own Slave<br />
address and one<br />
or more Data<br />
bytes all are<br />
acknowledged<br />
S<br />
SLA<br />
W A DATA A DATA<br />
A<br />
P PORS<br />
S<br />
01H<br />
0AH<br />
13H<br />
13H<br />
1DH<br />
Last data byte<br />
received is Not<br />
acknowledged<br />
A# A P PORS<br />
S<br />
13H<br />
reception of the<br />
General Call<br />
address and one<br />
or more Data<br />
bytes<br />
GENERAL CALL W A DATA A DATA<br />
A<br />
P PORS<br />
S<br />
0AH 13H 13H 1DH<br />
last data byte is<br />
Not acknowledged<br />
A# A P PORS<br />
S<br />
13H<br />
from Master to Slave<br />
from Slave to Master<br />
DATA<br />
A<br />
any number of data bytes and their associated Acknowledge bits<br />
n<br />
this number (contained in STAT) corresponds to a defined state of the TWS bus<br />
Figure 15-7: <br />
15.4.4 <br />
<br />
1<br />
SDA SCL <br />
TWS /<br />
TWS <br />
<br />
S SLAVE ADDRESS RW=1 A DATA A DATA A# P<br />
n bytes data received<br />
from Master to Slave<br />
from Slave to Master<br />
A = Acknowledge (SDA low)<br />
A# = Not acknowledge (SDA high)<br />
S = START condition<br />
P = STOP condition<br />
Figure 15-8: <br />
www.xinnovatech.com 237
XN62Lxxx<br />
reception of the<br />
own Slave<br />
address and one<br />
or more Data<br />
bytes all are<br />
acknowledged<br />
S<br />
SLA<br />
R A DATA A DATA A# A P PORS<br />
S<br />
4AH<br />
5CH<br />
1CH<br />
from Master to Slave<br />
from Slave to Master<br />
DATA<br />
A<br />
any number of data bytes and their associated Acknowledge bits<br />
n<br />
this number (contained in STAT) corresponds to a defined state of the TWS bus<br />
Figure 15-9: <br />
15.4.5 <br />
TWS <br />
XN62L <br />
TWS <br />
TWS <br />
SLVADDMATCHSLVRXBUFFULL SLVTXBUFEMPTY TWS <br />
TWS <br />
SLVADDMATCH 1 SLVRXBUFFULL <br />
1 <br />
TWS <br />
SLVTXBUFEMPTY 1 <br />
<br />
TWS<br />
<br />
SLVADDMATCH=1<br />
/<br />
SLVRXBUFFULL=1<br />
TWS<br />
DAT<br />
SLVTXBUFEMPTY=1<br />
<br />
DAT<br />
<br />
Figure 15-10: <br />
238 www.xinnovatech.com
XN62Lxxx<br />
15.4.6 <br />
TWS <br />
Table 15-14: <br />
TWS <br />
TWS <br />
/ DAT<br />
CON<br />
STA TXRX STO SI AA<br />
0x01<br />
<br />
SLA+W; <br />
X 1 0 0 X SLA+W ACK <br />
STA<br />
0x01<br />
<br />
SLA+W X 1 0 0 X .<br />
SLA+R;<br />
X 1 0 0 X SLA+RTWS<br />
STA<br />
0x0b<br />
SLA+W; 0 1 0 0 X <br />
ACK ACK<br />
DAT 1 1 0 0 X <br />
DAT 0 1 1 0 X <br />
STO <br />
DAT 1 1 1 0 X <br />
STO <br />
0x4b<br />
SLA+W<br />
0 1 0 0 X <br />
ACK ACK<br />
DAT 1 1 0 0 X <br />
DAT 0 1 1 0 X <br />
STO <br />
DAT 1 1 1 0 X <br />
STO <br />
0x14<br />
DAT <br />
0 1 0 0 X <br />
ACK <br />
ACK DAT 1 1 0 0 X <br />
DAT 0 1 1 0 X <br />
STO <br />
DAT 1 1 1 0 X <br />
STO <br />
0x54<br />
DAT <br />
0 1 0 0 X <br />
ACK <br />
ACK DAT 1 1 0 0 X <br />
DAT 0 1 1 0 X <br />
STO <br />
DAT 1 1 1 0 X <br />
STO <br />
Table 15-15: <br />
TWS <br />
TWS <br />
/ DAT<br />
CON<br />
STA TXRX STO SI AA<br />
0x01<br />
0x22<br />
<br />
SLA+R X 1 0 0 X SLA+W ACK <br />
<br />
SLA+R X 1 0 0 X <br />
SLA+W X 1 0 0 X SLA+WTWS<br />
www.xinnovatech.com 239
XN62Lxxx<br />
DAT 1 1 0 0 X <br />
0x0b<br />
SLA+W; <br />
DAT 0 0 0 0 0 <br />
ACK ACK<br />
DAT 0 0 0 0 1 <br />
ACK 0x4b<br />
SLA+W DAT 1 1 0 0 X <br />
ACK<br />
DAT 0 1 1 0 X <br />
STO <br />
DAT 1 1 1 0 X <br />
STO <br />
0x1d<br />
0 0 0 0 0 <br />
ACK 0 0 0 0 1 <br />
ACK 0x5d<br />
1 1 0 0 X <br />
0 X 1 0 X <br />
STO <br />
1 X 1 0 X <br />
STO <br />
Table 15-16:<br />
TWS <br />
TWS <br />
/ DAT<br />
CON<br />
STA TXRX STO SI AA<br />
0x0a<br />
<br />
SLA+W<br />
DAT X 0 0 0 0 <br />
ACK ACK<br />
DAT X 0 0 0 1 <br />
ACK 0x13<br />
<br />
X 0 0 0 0 <br />
ACK<br />
<br />
X 0 0 0 1 <br />
ACK<br />
ACK<br />
0x13<br />
<br />
0 0 0 0 0 <br />
SLV <br />
SLA<br />
<br />
0 0 0 0 1 <br />
SLV <br />
SLA<br />
<br />
ACK<br />
1 0 0 0 0 <br />
SLV <br />
SLA<br />
<br />
1 0 0 0 1 <br />
SLV <br />
SLA<br />
<br />
0x13<br />
<br />
X 0 0 0 0 <br />
ACK<br />
<br />
X 0 0 0 1 <br />
ACK<br />
ACK<br />
0x1d<br />
<br />
DAT 0 0 0 0 0 <br />
SLV <br />
SLA<br />
<br />
DAT 1 0 0 0 0 <br />
SLV <br />
SLA<br />
<br />
<br />
<br />
Table 15-17: <br />
TWS <br />
TWS <br />
/ DAT<br />
CON<br />
240 www.xinnovatech.com
XN62Lxxx<br />
STA TXRX STO SI AA<br />
0x4a<br />
<br />
SLA+W<br />
X 0 0 0 X <br />
ACK ACK<br />
0x5C<br />
DAT X 1 0 0 0 <br />
ACK ACK<br />
X 1 0 0 1 <br />
ACK 0x1C<br />
DAT DAT 0 1 0 0 0 <br />
SLV <br />
SLA<br />
<br />
ACK<br />
DAT 0 1 0 0 1 <br />
SLV <br />
SLA<br />
DAT 1 1 0 0 0 <br />
SLV <br />
SLA<br />
<br />
DAT 1 1 0 0 1 <br />
SLV <br />
SLA<br />
<br />
0x1C<br />
DAT DAT 0 X 0 0 X <br />
SLV <br />
SLA<br />
(AA = 0) DAT 1 X 0 0 X <br />
SLV <br />
SLA<br />
ACK<br />
<br />
15.4.7 TWS<br />
<br />
TWS <br />
• TWS<br />
• TWS <br />
• TWS <br />
13<br />
15.4.7.1 <br />
TWS <br />
1. ADR<br />
2. T WS <br />
3. CONSET<br />
0x42 EN MASL <br />
0x40<br />
15.4.7.2 <br />
<br />
1. <br />
2. <br />
3. CONSET 0x20 STA<br />
4. <br />
5. <br />
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XN62Lxxx<br />
15.4.7.3 <br />
<br />
<br />
1. <br />
2. <br />
3. CONSET 0x20 STA<br />
4. <br />
5. <br />
6. <br />
15.4.7.4 TWS <br />
TWS <br />
• STA TWS <br />
• 13<br />
15.4.7.5 <br />
: 0x01<br />
<br />
SLA+R/W ACK<br />
1. DAT R/W<br />
2. CONSET 0x04 AA<br />
3. CONCLR 0x08 SI <br />
4. <br />
5. <br />
6. <br />
7. <br />
: 0x0b<br />
<br />
R/W ACK 1. DAT R/W<br />
2. CONSET 0x04 AA TXRX .<br />
3. CONCLR 0x08 SI <br />
4. <br />
5. <br />
6. <br />
7. <br />
242 www.xinnovatech.com
XN62Lxxx<br />
15.4.7.6 <br />
: 0x0b<br />
0x01<br />
ACK<br />
1. DAT<br />
2. CONCLR 0x08 SI <br />
3. 1<br />
4. <br />
: 0x4b<br />
<br />
ACK<br />
1. CONSET 0x14 STO AA <br />
2. CONCLR 0x08 SI <br />
3. <br />
: 0x14<br />
<br />
ACK<br />
1. 1<br />
5<br />
2. 11<br />
3. CONSET 0x14 STO AA <br />
4. CONCLR 0x08 SI <br />
5. <br />
6. DAT<br />
7. CONSET 0x 04 AA<br />
8. CONCLR 0x08 SI <br />
9. 1<br />
10. <br />
11. CONSET STA MASL <br />
12. +R<br />
13. CONCLR 0x0 8 SI <br />
14. <br />
: 0x54<br />
<br />
ACK<br />
1. CONSET 0x14 STO AA <br />
2. CONCLR 0x08 SI <br />
www.xinnovatech.com 243
XN62Lxxx<br />
3. <br />
15.4.7.7 <br />
: 0x0b<br />
0x01<br />
ACK<br />
1. CONCLR 0x0 9 SI TXRX <br />
2. <br />
: 0x1b<br />
<br />
ACK<br />
1. CONSET 0x14 STO AA <br />
2. CONCLR 0x08 SI <br />
3. <br />
: 0x1d<br />
<br />
ACK DAT <br />
ACK<br />
ACK<br />
1. DAT<br />
2. 1<br />
5<br />
3. CONCLR 0x0C SI AA<br />
4. CONSET 0x1 0 STO<br />
4. <br />
5. CONCLR 0x08 SI <br />
6. 1<br />
7. <br />
: 0x5d<br />
<br />
ACK DAT <br />
1. DAT<br />
2. CONSET 0x14 STO AA <br />
3. CONCLR 0x08 SI <br />
4. <br />
15.4.7.8 <br />
: 0x0a<br />
<br />
SLA+W ACK<br />
244 www.xinnovatech.com
XN62Lxxx<br />
1. CONCLR 0x08 SI <br />
2. <br />
3. <br />
4. <br />
: 0x13<br />
<br />
ACK<br />
1. DAT<br />
2. 1<br />
5<br />
3. CONCLR 0x0C SI AA<br />
4. .<br />
5. CONCLR 0x08 SI <br />
6. 1<br />
7. <br />
: 0x13<br />
<br />
ACK<br />
1. CONCLR 0x08 SI <br />
2. <br />
: 0x1d<br />
<br />
1. CONCLR 0x08 SI <br />
2. <br />
15.4.7.9 <br />
: 0x4a<br />
<br />
ACK<br />
1. DAT<br />
2. CONCLR 0x09 SI TXRX<br />
3. <br />
4. 1<br />
5. <br />
: 0x5c<br />
<br />
ACK<br />
1. DAT<br />
.<br />
www.xinnovatech.com 245
XN62Lxxx<br />
2. CONCLR 0x08 SI <br />
3. 1<br />
4. <br />
: 0x1c<br />
<br />
ACK<br />
1. CONCLR 0x08 SI <br />
2. .<br />
246 www.xinnovatech.com
XN62Lxxx<br />
16 RTC<br />
16.1 <br />
1 Hz/1KHz RTC<br />
<br />
RTC • 32 kHz<br />
• 1 1KHz<br />
<br />
• 32RTC<br />
• <br />
16.2 <br />
Table 16-1: RTC <br />
<br />
RTCXIN 32 kHz <br />
RTCXOUT 32 kHz <br />
16.3 RTC <br />
Table 16-2: RTC <br />
( 0x4005 0000)<br />
<br />
DR R 0x000 0x00<br />
MR R/W 0x004 0x00<br />
LR R/W 0x008 0x00<br />
CR R/W 0x00C 0x00<br />
ICSC R/W 0x010 <br />
0x00<br />
RIS R 0x014 0x00<br />
MIS R 0x018 <br />
ICR W 0x01C <br />
0x00<br />
0x00<br />
16.3.1 RTC <br />
Table 16-3: RTC <br />
(DR - 0x4005 0000) <br />
<br />
31:0 DATA <br />
. 0x00<br />
16.3.2 RTC <br />
Table 16-4: RTC <br />
(MR - 0x4005 0004) <br />
www.xinnovatech.com 247
XN62Lxxx<br />
<br />
31:0 MATCH RTC <br />
. 0x00<br />
16.3.3 RTC <br />
Table 16-5: RTC <br />
(LR - 0x4005 0008) <br />
<br />
31:0 RTC <br />
. 0x00<br />
16.3.4 RTC <br />
/<br />
(R/W) <br />
RTC <br />
RTC<br />
<br />
0 <br />
Table 16-6: RTC <br />
(CR - 0x4005 000C) <br />
<br />
0 RTCSTART RTC <br />
RTC <br />
0x0<br />
(POR) <br />
0 RTC .<br />
1 RTC <br />
31:1 - - . -<br />
16.3.5 RTC <br />
R/W <br />
RTC <br />
RTC <br />
Table 16-7: RTC Mask (ICSC - 0x4005 0010) <br />
<br />
0 RTCIC <br />
RTC 0x0<br />
0 0 <br />
1 1 <br />
31:1 - - . 0x0<br />
16.3.6 RTC <br />
(RO)<br />
<br />
Table 16-8: RTC <br />
(RIS - 0x4005 0014) <br />
<br />
0 RTCRIS <br />
0x0<br />
31:1 - . 0x0<br />
248 www.xinnovatech.com
XN62Lxxx<br />
16.3.7 RTC<br />
<br />
Table 16-9: RTC <br />
(MIS - 0x4005 0018) <br />
<br />
0 RTCMIS <br />
ICR <br />
0x0<br />
31:1 . Read as zero. 0x0<br />
16.3.8 RTC <br />
<br />
1 <br />
0 Table 12-16-10: RTC <br />
(ICR - 0x4005 001C) <br />
<br />
0 RTCICR <br />
1 <br />
0 0x0<br />
31:1 . 0x0<br />
16.4 <br />
RTC<br />
Deep-sleep Power-down<br />
RTC <br />
RTC <br />
RTC RTC<br />
<br />
: RTC<br />
RTC “<br />
”RTC<br />
www.xinnovatech.com 249
XN62Lxxx<br />
17 ADC/DAC<br />
17.1 <br />
XN62L 3 12 ADC 1 10 DAC <br />
<br />
• 3 1M Hz 1 2 A/D <br />
• ADC 8 AD <br />
• 12 A/D <br />
• <br />
• ADC 0 ~ V REF_ADC.<br />
• <br />
ADC • ADC -.<br />
• ADC 8 <br />
• -40°C<br />
+120°C <br />
• 1M Hz D/A <br />
RESULT0<br />
AD0<br />
AD1<br />
AD2<br />
AD3<br />
12bit<br />
ADC0<br />
RESULT1<br />
RESULT2<br />
RESULT3<br />
RESULT4<br />
RESULT5<br />
HILMT<br />
CHNSEL0<br />
DMA, iterrupt<br />
request<br />
RESULT6<br />
AD4<br />
AD5<br />
AD6<br />
AD7<br />
4,5,6<br />
12bit<br />
ADC1<br />
RESULT7<br />
HILMT<br />
CHNSEL1<br />
HILMT0<br />
><br />
Interrupt<br />
enable<br />
Interrupt<br />
AD8<br />
AD9<br />
AD10<br />
AD11<br />
12bit<br />
ADC2<br />
Temperature<br />
sensor<br />
LOLMT<br />
CHNSEL0<br />
HILMT1<br />
><br />
LOLMT0<br />
<<br />
Interrupt<br />
PWM<br />
PWM Fault<br />
LOLMT1<br />
<<br />
enable<br />
or<br />
LOLMT<br />
CHNSEL0<br />
Figure 17-1: ADC <br />
250 www.xinnovatech.com
XN62Lxxx<br />
17.2 <br />
Table 17-1: ADC <br />
<br />
AD0~AD11 <br />
ADC <br />
V REF_ADC 3.3 V .<br />
DA0 <br />
V REF_ADC ADC <br />
17.3 <br />
Table 17-2: ADC <br />
(ADC0: 0x4002 0000; ADC1: 0x4006 4000; ADC2: 0x4006 8000)<br />
<br />
<br />
CR R/W 0x000 ADC <br />
CR <br />
0x0<br />
GDR R/W 0x004 ADC <br />
ADC NA<br />
CHSEL R/W 0x008 0x0<br />
INTEN R/W 0x00C ADC <br />
<br />
ADC <br />
DONE ADC 0x0000<br />
<br />
0100<br />
DR0 R/W 0x010 A/D <br />
0<br />
CHSEL SEL0 <br />
NA<br />
DR1 R/W 0x014 A/D <br />
1<br />
CHSEL SEL1 <br />
NA<br />
DR2 R/W 0x018 A/D <br />
2<br />
CHSEL SEL2 <br />
NA<br />
DR3 R/W 0x01C A/D <br />
3<br />
CHSEL SEL3 <br />
NA<br />
DR4 R/W 0x020 A/D <br />
4.<br />
CHSEL SEL4 <br />
NA<br />
DR5 R/W 0x024 A/D <br />
5<br />
CHSEL SEL5 <br />
NA<br />
DR6 R/W 0x028 A/D <br />
6<br />
CHSEL SEL6 <br />
NA<br />
DR7 R/W 0x02C A/D <br />
7<br />
CHSEL SEL7 <br />
NA<br />
: ADC1 DR7 <br />
INTSTAT RO 0x030 ADC <br />
<br />
DONE OVERRUN <br />
0<br />
HILMT R/W 0x034 ADC <br />
0<br />
LOLMT R/W 0x038 ADC <br />
0<br />
- - 0x03C 0<br />
SSCR R/W 0x040 0<br />
Table 17-3: DAC <br />
( 0x4006 C000)<br />
<br />
<br />
DACCTL R/W 0x00 D/A <br />
. 0<br />
DACBUF W 0x04 DA NA<br />
17.3.1 ADC <br />
ADC <br />
A/D <br />
www.xinnovatech.com 251
XN62Lxxx<br />
Table 17-4: A/D <br />
(CR) <br />
<br />
7:0 0x0<br />
15:8 CLKDIV A/D ADC<br />
(PCLK) ADC<br />
0x0<br />
<br />
16MHz ADC 16 ADC <br />
1MHz<br />
16 BURST ADC 0<br />
0 <br />
ADC START <br />
ADC <br />
DR <br />
1 <br />
1 START 0 ADC <br />
ADC <br />
DR <br />
ADC 23:17 - - . 0x0<br />
27:24 START ADC <br />
ADC ADC 0x0<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
0x8<br />
0x9<br />
0xa<br />
<br />
<br />
CT16B0_CAP0 <br />
28 CT16B0_CAP1 <br />
28 CT32B0_MAT0 <br />
28 CT32B1_MAT0 <br />
28 CT16B0_MAT0 <br />
28 CT16B1_MAT0 <br />
28 PWM0 <br />
PWM1 <br />
PWM2 <br />
28 EDGE 0<br />
0 <br />
1 <br />
29 SCMODE ADC 0<br />
0 <br />
1 <br />
1<br />
31:30 - - . 0x0<br />
17.3.2 ADC <br />
<br />
ADC <br />
Table 17-5: A/D <br />
(GDR) <br />
252 www.xinnovatech.com
XN62Lxxx<br />
11:0 RESULT DONE 1 <br />
SELNO <br />
A/D X<br />
0 <br />
V SS;<br />
0xFFF <br />
V REF_ADC<br />
14:12 SELNO <br />
0 CHSEL)<br />
SEL0 A/D <br />
1 000<br />
CHSEL) SEL1 A/D <br />
15 OVERRUN 1 <br />
A/D <br />
0<br />
16 DONE 1 A/D <br />
0<br />
31:17 - NA<br />
17.3.3 ADC <br />
<br />
AD ADC <br />
8 AD <br />
12 AD0~AD11 <br />
ADC0~3 0~7 <br />
AD0~AD7 <br />
ADC0 0~7 <br />
AD0~AD6<br />
ADC1 0~7 <br />
AD4~AD11 <br />
ADC2 0~7 <br />
Table 17-6: A/D <br />
(CHSEL) <br />
<br />
0 SEL0EN SEL0 A/D 0<br />
0 SEL0 A/D <br />
1 SEL0 A/D <br />
3:1 SEL0 AD ADC <br />
DR0 ADC 0~7 000<br />
<br />
4 SEL1EN SEL1 A/D 0<br />
0 SEL1 A/D <br />
1 SEL1 A/D <br />
7:5 SEL1 AD ADC <br />
DR1 ADC 0~7 000<br />
<br />
8 SEL2EN SEL2 A/D 0<br />
0 SEL2 A/D <br />
1 SEL2 A/D <br />
11:9 SEL2 AD ADC <br />
DR2 ADC 0~7 000<br />
<br />
12 SEL3EN SEL3 A/D 0<br />
0 SEL3 A/D <br />
1 SEL3 A/D <br />
15:13 SEL3 AD ADC <br />
DR3 ADC 0~7 000<br />
<br />
16 SEL4EN SEL4 A/D 0<br />
0 SEL4 A/D <br />
1 SEL4 A/D <br />
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XN62Lxxx<br />
19:17 SEL4 AD ADC <br />
DR4 ADC 0~7 000<br />
<br />
20 SEL5EN SEL5 A/D 0<br />
0 SEL5 A/D <br />
1 SEL5 A/D <br />
23:21 SEL5 AD ADC <br />
DR5 ADC 0~7 000<br />
<br />
24 SEL6EN SEL6 A/D 0<br />
0 SEL6 A/D <br />
1 SEL6 A/D <br />
27:25 SEL6 AD ADC <br />
DR6 ADC 0~7 000<br />
<br />
28 SEL7EN SEL7 A/D 0<br />
0 SEL7 A/D <br />
1 SEL7 A/D <br />
31:29 SEL7 AD ADC <br />
DR7 ADC 0~7 000<br />
<br />
17.3.4 ADC <br />
<br />
A/D <br />
A/D <br />
A/D Table 17-7:: A/D <br />
(INTEN) <br />
<br />
7:0 INTEN 0 7 <br />
SEL0 SEL7 A/D <br />
0x00<br />
0 <br />
1 A/D <br />
8 GINTEN 1 ADC DONE <br />
0 <br />
INTEN 7:0 1<br />
A/D <br />
31:9 - . NA<br />
17.3.5 ADC<br />
ADC <br />
A/D <br />
Table 17-8: A/D <br />
(DR0 ~ DR7) <br />
<br />
11:0 RESULT DONE 1 <br />
SELn ADn X<br />
<br />
V REF_ADC V/V<br />
REF_ADC 0 ADn <br />
<br />
V SS 0xFFF ADn <br />
V REF_ADC<br />
29:12 - . 0x0<br />
30 OVERRUN <br />
RESULT <br />
0<br />
1<br />
254 www.xinnovatech.com
XN62Lxxx<br />
31 DONE A/D <br />
1 0<br />
17.3.6 ADC<br />
A/D <br />
A/D A/D DRn DONE OVERRUN <br />
STAT STAT <br />
DONE “ ” A/D <br />
Table 17-9: A/D <br />
(STAT) <br />
<br />
7:0 DONE 0 7 <br />
SEL0 SEL7 A/D DONE 0<br />
15:8 OVERRUN 0 7 <br />
SEL0 SEL7 A/D OVERRRUN 0<br />
<br />
16 ADINT A/D <br />
A/D Done 1 A/D <br />
0<br />
INTEN <br />
1<br />
17 HILMTFLAG0 0 <br />
0 1 1 0<br />
18 HILMTFLAG1 1 <br />
1 1 1 0<br />
19 LOLMTFLAG0 0 <br />
0 1 1 0<br />
20 LOLMTFLAG1 1 <br />
1 1 1 0<br />
21 ADCRDY 1 ADC 0<br />
31:22 - . 0x0<br />
17.3.7 <br />
<br />
A/D <br />
A/D <br />
ADC <br />
Table 17-10: (<br />
HILMT) <br />
<br />
11:0 HILMT0 0~0xFFF 0 . 0<br />
14:12 CHNSEL0 0~7 0 0~7<br />
<br />
SEL0~SEL7<br />
0<br />
HILMT0 <br />
15 INTEN0 0 <br />
0<br />
0 <br />
1 <br />
27:16 HILMT1 0~0xFFF 1 . 0<br />
30:28 CHNSEL1 0~7 1 0~7<br />
<br />
SEL0~SEL7<br />
0<br />
HILMT1 <br />
31 INTEN1 1 <br />
0<br />
0 <br />
1 <br />
www.xinnovatech.com 255
XN62Lxxx<br />
17.3.8 <br />
<br />
A/D <br />
A/D <br />
ADC <br />
Table 17-11: <br />
(LOLMT) <br />
11:0 LOLMT0 0~0xFFF 0 . 0<br />
14:12 CHNSEL0 0~7 0 0~7<br />
<br />
SEL0~SEL7<br />
0<br />
HILMT0 <br />
15 INTEN0 0 <br />
0<br />
0 <br />
1 <br />
27:16 LOLMT1 0~0xFFF 1 . 0<br />
30:28 CHNSEL1 0~7 1 0~7<br />
<br />
SEL0~SEL7<br />
0<br />
HILMT1 <br />
31 INTEN1 1 <br />
0<br />
0 <br />
1 <br />
17.3.9 <br />
<br />
ADC Table 17-12: <br />
(SSCR) <br />
0 ADCTRIG - 1 ADC 0<br />
31:2 - - . 0<br />
17.3.10 D/A <br />
D/A <br />
D/A <br />
Table 17-13: D/A (DACCTL) <br />
<br />
7:0 DACDIVIDER DACDIVIDER D/A <br />
1MHz<br />
0<br />
=PCLK/DACDIVIDER<br />
8 DACMODE DA <br />
0<br />
<br />
DAC <br />
<br />
4 <br />
0 <br />
1 <br />
256 www.xinnovatech.com
XN62Lxxx<br />
9 DACCLR <br />
0 1 <br />
0<br />
<br />
0 <br />
10 DACINTEN DAC <br />
DAC <br />
0<br />
0x0<br />
0x1<br />
<br />
<br />
11 DACDMAEN DAC DMA . DAC <br />
DMA 0x0<br />
0x1<br />
DMA <br />
DMA <br />
12 DACEN DAC <br />
0x0<br />
0x1<br />
DAC <br />
DAC <br />
14:13 - NA<br />
15 DACBUFSTAT DAC 0<br />
0 <br />
1 <br />
31:16 - . 0<br />
17.3.11 D/A <br />
Table 17-14: D/A <br />
(DACBUF) <br />
<br />
9:0 DACBUF 10 0<br />
31:10 - . 0<br />
17.4 <br />
17.4.1 <br />
ADC A/D<br />
ADC <br />
8 A/D <br />
12 <br />
8 <br />
CHSEL<br />
<br />
A/D <br />
A/D <br />
SEL0 SEL7 SEL0 SEL7<br />
<br />
Table 17-15: ADC <br />
ADC0 ADC1 ADC2<br />
AD ADC AD ADC AD ADC <br />
AD0 0 AD0 0 AD4 0<br />
AD1 1 AD1 1 AD5 1<br />
AD2 2 AD2 2 AD6 2<br />
AD3 3 AD3 3 AD7 3<br />
AD4 4 AD4 4 AD8 4<br />
AD5 5 AD5 5 AD9 5<br />
www.xinnovatech.com 257
XN62Lxxx<br />
AD6 6 AD6 6 AD10 6<br />
AD7 7 <br />
7 AD11 7<br />
17.4.2 ADC <br />
ADC <br />
A/D <br />
<br />
ADC <br />
ADC <br />
ADC (CAP)<br />
MAT<br />
PWM (CA<br />
MAT <br />
CR EDGE 17.4.3 <br />
A/D <br />
DONE 1<br />
<br />
DONE DRn <br />
ADC 17.4.4 ADC DMA<br />
DMA ADC <br />
DMA <br />
: DMA NVIC ADC <br />
DMA <br />
DMA DMA <br />
17.4.5 DAC DMA<br />
ADC DMA DAC <br />
DMA <br />
: DMA NVIC DAC <br />
DMA <br />
DMA DMA <br />
17.4.6 <br />
<br />
ADC1 SEL7 ADC1 DR7 <br />
<br />
ADC <br />
Figure 17-2 <br />
0ºC AD <br />
<br />
= (<br />
- 0ºC ) * <br />
258 www.xinnovatech.com
XN62Lxxx<br />
Temperature<br />
Slope(°C LSB Value)<br />
Offset(0°C LSB Value)<br />
`<br />
Offset(0°C LSB Value)<br />
LSB<br />
Figure 17-2: <br />
XN62L:<br />
• 0x 07- (ºC / LSB, fixed-point Q15 format)<br />
• 0x 1657 – (0 AD ºC )<br />
<br />
3.3v <br />
3.3v<br />
<br />
3 1. ADC1 <br />
2. ADC <br />
3. ADC <br />
ºC<br />
www.xinnovatech.com 259
XN62Lxxx<br />
18 <br />
18.1 <br />
<br />
DA <br />
6 1 DA <br />
0<br />
1 <br />
<br />
• <br />
• <br />
10 DA <br />
• <br />
32 <br />
• <br />
I/O <br />
NVIC<br />
• <br />
AN ALOGLOGIC<br />
CMPn_LEVEL<br />
VDD(3V3)<br />
32<br />
+<br />
-<br />
DIGITAL LOGIC<br />
C0_OUT<br />
CMP0_LEVEL<br />
C0_IN[0:5]<br />
DA Output<br />
C1_IN[0:5]<br />
6<br />
6<br />
+<br />
-<br />
C1_OUT<br />
CMP1_LEVEL<br />
sync<br />
INT<br />
14<br />
APB REGISTERS<br />
6<br />
CMP_REG<br />
7<br />
edge detect<br />
CMP0_EDGE<br />
CMP1_EDGE<br />
VLAD_REG<br />
APB INTERFACE<br />
PCLK<br />
Figure 18-1: <br />
18.2 <br />
Table 18-1: <br />
<br />
ACMP0_I[3:0] 0 ACMP0_I[0] ACMP0_I[1] 1 <br />
ACMP1_I[3:0] 1 ACMP1_I[0] ACMP1_I[1] 0 <br />
260 www.xinnovatech.com
XN62Lxxx<br />
ACMP0_O 0 <br />
ACMP1_O 1 <br />
18.3 <br />
Table 18-2: <br />
: ( 0x4005 4000)<br />
<br />
CCR R/W 0x00 0<br />
VLAD R/W 0x04 <br />
0<br />
- - 0x08 NA<br />
INTSTA R/W 0x0C 0<br />
18.3.1 <br />
<br />
Table 18-3: <br />
(CCR, 0x4005 4000) <br />
<br />
0 CMP0_EN 0 0<br />
0 0 <br />
1 0 <br />
1 CMP1_EN 1 0<br />
0 1 <br />
1 1 <br />
2 CMPIL 0<br />
0 <br />
1 <br />
3 CMPIEV 0<br />
0 <br />
1 <br />
4 CMPBE 0<br />
0 <br />
1 <br />
5 CMP1_INTEN 1 0<br />
6 CMP0_INTEN 0 0<br />
7 CMPSA <br />
/ 0<br />
0 <br />
1 <br />
10:8 CMP0_VP_CTRL 0 000<br />
0x0<br />
<br />
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XN62Lxxx<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
ACMP0_I0<br />
ACMP0_I1<br />
ACMP0_I2<br />
ACMP0_I3<br />
ACMP1_I0<br />
ACMP1_I1<br />
DA <br />
13:11 CMP0_VM_CTRL 0 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
<br />
ACMP0_I0<br />
ACMP0_I1<br />
ACMP0_I2<br />
ACMP0_I3<br />
ACMP1_I0<br />
ACMP1_I1<br />
DA <br />
16:14 CMP1_VP_CTRL 1 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
<br />
ACMP1_I0<br />
ACMP1_I1<br />
ACMP1_I2<br />
ACMP1_I3<br />
ACMP0_I0<br />
ACMP0_I1<br />
DA <br />
19:17 CMP1_VM_CTRL 0 000<br />
0x0<br />
0x1<br />
0x2<br />
0x3<br />
0x4<br />
0x5<br />
0x6<br />
0x7<br />
<br />
ACMP1_I0<br />
ACMP1_I1<br />
ACMP1_I2<br />
ACMP1_I3<br />
ACMP0_I0<br />
ACMP0_I1<br />
DA <br />
21:20 - - NA<br />
22 CMP0_DMAEN - 0 DMA 0<br />
23 CMP1_DMAEN - 1 DMA 0<br />
24 CMP0_PO - 0 0<br />
25 CMP1_PO - 1 0<br />
27:26 - - NA<br />
262 www.xinnovatech.com
XN62Lxxx<br />
28 CMP0_RLT - 0 0<br />
29 CMP1_RLT - 1 0<br />
31:30 - - . 0<br />
18.3.2 <br />
<br />
V REF 32 V SS 1.8V/3.3 V<br />
Table 18-4: <br />
(VLAD, 0x4005 4004) <br />
<br />
0 VLADEN 0<br />
0 <br />
1 <br />
5:1 VSEL <br />
VLADREF <br />
6 d<br />
00000 = V SS<br />
00001 = 1 × VLADREF /31<br />
00010 = 2 × VLADREF /31<br />
...<br />
11111 = VLADREF<br />
6 VLADREF 0<br />
0 1.8v<br />
1 V DD(3V3) <br />
7 - - 0<br />
15:8 DIV 0<br />
0 <br />
1~255 <br />
31:16 - - NA<br />
0<br />
18.3.3 <br />
Table 18-5: <br />
(INTSTA, 0x4005 400C) <br />
<br />
0 CMP0_INT 0 <br />
1 0<br />
1 CMP1_INT 1 <br />
1 0<br />
31:2 - NA<br />
18.4 <br />
18.4.1 <br />
<br />
8 <br />
CMP <br />
0<br />
7<br />
DA<br />
www.xinnovatech.com 263
XN62Lxxx<br />
<br />
6 <br />
IO <br />
IO <br />
ACMP1_I4 ACMP1_I5 ACMP0_I0<br />
ACMP0_I1<br />
ACMP0_I4 ACMP0_I5 <br />
ACMP1_I0 ACMP1_I1 <br />
VDD(3V3)<br />
C0_IN0<br />
C0_IN1<br />
AN ALOGLOGIC<br />
C0_IN2<br />
C0_IN3<br />
32<br />
+<br />
-<br />
C1_IN0<br />
C1_IN1<br />
6<br />
6<br />
6<br />
6<br />
+<br />
-<br />
C1_IN2<br />
C1_IN4<br />
C1_IN5<br />
C1_IN3<br />
Output From DA<br />
Figure 18-2: <br />
18.4.2 <br />
<br />
CPU CLINT <br />
18.4.3 <br />
<br />
16 <br />
• <br />
PCLK <br />
• <br />
<br />
16 <br />
• 16 0 (CT16B0)<br />
– 3 0 <br />
264 www.xinnovatech.com
XN62Lxxx<br />
– 2 0 <br />
• 16 1 (CT16B1)<br />
– 3 1 <br />
– 2 1 <br />
<br />
<br />
www.xinnovatech.com 265
XN62Lxxx<br />
19 DMA<br />
19.1 <br />
XN62L DMA AMBA AHB-Lite <br />
DMA DMA APB <br />
DMA <br />
<br />
SYSAHBCLKDIV DMA<br />
<br />
AHB <br />
12 <br />
• AHB-Lite 32 <br />
• 28 DMA <br />
• <br />
• <br />
DMA <br />
• <br />
• DMA <br />
DMA <br />
• DMA <br />
• <br />
• AHB-Lite <br />
DMA <br />
• <br />
• DMA <br />
1 1024 <br />
• <br />
19.2 DMA<br />
DMA APB <br />
AHB AHB-Lite <br />
DMA <br />
DMA Controller<br />
configuration<br />
control<br />
APB BUS<br />
APB<br />
REGISTER<br />
INTERFACE<br />
requests<br />
DMA stall<br />
DMA<br />
CONTROL<br />
AHB-Lite<br />
MASTER<br />
INTERFACE<br />
APB BUS<br />
DMA data<br />
transfer<br />
mode<br />
active channel<br />
channel done<br />
error<br />
Figure 19-1: DMA <br />
266 www.xinnovatech.com
XN62Lxxx<br />
DMA 816 32 <br />
DMA <br />
<br />
32 DMA <br />
• <br />
• <br />
• <br />
• AHB-Lite <br />
• <br />
DMA • DMA <br />
• <br />
DMA • <br />
DMA – <br />
– <br />
– <br />
19.3 DMA<br />
DMA <br />
SRAM <br />
DMA <br />
19.4 DMA <br />
DMA <br />
DMA Table 19-1: DMA <br />
DMA DMA <br />
DMA <br />
UART0 TX 0 <br />
UART0 RX 1 <br />
UART1 TX 2 <br />
UART1 RX 3 <br />
SPI TX 4 <br />
SPI RX 5 <br />
ADC 0 6 <br />
RTC 7 <br />
32 0 0 8 <br />
32 0 1 9 <br />
32 1 0 10 <br />
32 1 1 11 <br />
www.xinnovatech.com 267
XN62Lxxx<br />
16 0 0 12 <br />
16 1 0 13 <br />
0 14 <br />
1 15 <br />
PIO 0 16 <br />
PIO 1 17 <br />
PIO 2 18 <br />
DAC 19 <br />
xDSP0 20 <br />
xDSP1 21 <br />
ADC1 22 <br />
ADC2 23 <br />
UART2 TX 24 <br />
UART2 RX 25 <br />
UART3 TX 26 <br />
UART3 RX 27 <br />
19.5 DMA<br />
Table 19-2: <br />
: DMA ( 0x4004 C000)<br />
<br />
DMA_STATUS RO 0x000 DMA -<br />
DMA_CFG WO 0x004 DMA -<br />
CTRL_BASE_PTR R/W 0x008 <br />
0x0000 0000<br />
- - 0x00C-0x010 -<br />
CHNL_SW_REQUEST WO 0x014 -<br />
CHNL_USEBURST_SET R/W 0x018 0x0000 0000<br />
CHNL_USEBURST_CLR WO 0x01C -<br />
CHNL_REQ_MASK_SET R/W 0x020 0x0000 0000<br />
CHNL_REQ_MASK_CLR WO 0x024 -<br />
CHNL_ENABLE_SET R/W 0x028 0x0000 0000<br />
CHNL_ENABLE_CLR WO 0x02C -<br />
- - 0x030-0x034 -<br />
CHNL_PRIORITY_SET R/W 0x038 <br />
0x0000 0000<br />
CHNL_PRIORITY_CLR WO 0x03C <br />
-<br />
- - 0x040 - 0x07C -<br />
CHNL_IRQ_STATUS R/W 0x080 DMA <br />
0x0000 0000<br />
- - 0x084 -<br />
CHNL_IRQ_ENABLE R/W 0x088 DMA <br />
0x0000 0000<br />
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XN62Lxxx<br />
19.5.1 DMA <br />
<br />
DMA Table 19-3: DMA <br />
(DMA_STATUS, 0x4004 C000) <br />
<br />
0 MASTER_EN <br />
0<br />
0 = <br />
1 = <br />
3:1 - . 0<br />
7:4 STATE <br />
0<br />
0000 = <br />
0001 =<br />
0010 =<br />
0011 =<br />
0100 =<br />
0101 =<br />
0110 = DMA <br />
0111 =<br />
1000 =<br />
1001 =<br />
1010 =- <br />
1011-1111 =<br />
5:31 - . NA<br />
19.5.2 DMA <br />
<br />
DMA Table 19-4: DMA <br />
(DMA_CFG, 0x4004 C004) <br />
<br />
0 MASTER_EN DMA 0<br />
0 DMA <br />
1 DMA <br />
31:1 - - . NA<br />
19.5.3 <br />
/<br />
<br />
SRAM DMA <br />
<br />
Table 19-5: <br />
(CTRL_BASE_PTR, 0x4004 C008)<br />
www.xinnovatech.com 269
XN62Lxxx<br />
<br />
31:0 CTRL_BASE_PTR DMA 0x0<br />
19.5.4 <br />
c -27) DMA DMA<br />
(c = 0 <br />
<br />
Table 19-6: <br />
(CHNL_SW_REQUEST, 0x4004 C014) <br />
<br />
27:0 DMA_SW_ REQUEST <br />
DMA :<br />
0<br />
[c] = 0: <br />
[c] = 1: <br />
c DMA <br />
31:28 - . NA<br />
19.5.5 <br />
/<br />
<br />
c (c = 0-27) DMA (dma_sreq[c]) <br />
dma_req[c] <br />
Table 19-7: <br />
(CHNL_USEBURST_SET, 0x4004 C018) <br />
<br />
27:0 DMA_USEBURST_<br />
SET<br />
c (c = 0-27) <br />
dma_sreq[c] DMA 0x0<br />
<br />
[c] = 0DMA c dma_req[c] dma_sreq[c]<br />
2 R <br />
[c] = 1DMA c <br />
dma_sreq[c] <br />
dma_req[c] 2 R <br />
<br />
[c] = 0<br />
CHNL_USEBURST_CLR [c]<br />
0<br />
[c] = 1 dma_sreq[C] DMA <br />
2 R 31:28 - . NA<br />
19.5.6 <br />
<br />
c DMA c -27dma_sreq[c]<br />
= 0 <br />
Table 19-8: <br />
(CHNL_USEBURST_CLR, 0x4004 C01C) <br />
<br />
27:0 CHNL_USEBURST_ CLR <br />
dma_sreq[c] <br />
-<br />
<br />
[c] = 0<br />
chnl_useburst_set dma_sreq[c] <br />
270 www.xinnovatech.com
XN62Lxxx<br />
<br />
[c] = 1 dma_sreq[c] DMA <br />
31:28 - . NA<br />
19.5.7 <br />
/<br />
<br />
c (c = 0-27) DMA dma_req[c] DMA (dma_sreqc[c])<br />
<br />
dma_req[c]dma_sreq[c]<br />
Table 19-9: <br />
(CHNL_REQ_MASK_SET, 0x4004 C020) <br />
<br />
27:0 CHNL_REQ_ MASK_SET dma_req[c] dma_sreq[c] <br />
0x0<br />
DMA <br />
<br />
[c] = 0 c <br />
[c] = 1 c <br />
<br />
[c] = 0 CHNL_REQ_MASK_CLR DMA <br />
[c] = 1 dma_req[c] dma_sreq[c] DMA <br />
31:28 - . NA<br />
19.5.8 <br />
<br />
c (c = 0-27) dma_req[c] dma_sreq[c] <br />
Table 19-10: Channel Request Mask Clear (CHNL_REQ_MASK_CLR, 0x4004 C024) <br />
<br />
27:0 CHNL_REQ_ MASK_CLR <br />
dma_req[c] dma_sreq[c] -<br />
DMA <br />
<br />
[c] = 0<br />
chnl_req_mask_set dma_req[c]<br />
dma_sreq[c] <br />
[c] = 1 dma_req[c] dma_sreq[c] DMA <br />
31:28 - . NA<br />
19.6 <br />
/<br />
<br />
DMA c (c = 0-27)<br />
Table 19-11: <br />
(CHNL_ENABLE_SET, 0x4004 C028) <br />
<br />
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XN62Lxxx<br />
27:0 CHNL_ENABLE_ SET 0x0<br />
<br />
[c] = 0 c <br />
[c] = 1 c <br />
<br />
[c] = 0<br />
CHNL_ENABLE_CLR <br />
[c] = 1 c<br />
31:28 . -<br />
19.6.1 <br />
<br />
<br />
DMA <br />
• DMA <br />
• cycle_ctrl = 000 channel_cfg <br />
• AHB-Lite <br />
Table 19-12: <br />
(CHNL_ENABLE_CLR, 0x4004 C02C) <br />
<br />
27:0 CHNL_ENABLE_ CLR <br />
DMA <br />
-<br />
<br />
[c] = 0<br />
CHNL_ENABLE_SET DMA <br />
[c] = 1<br />
c<br />
31:24 - . NA<br />
19.6.2 <br />
/<br />
<br />
DMA c (c = 0-27) <br />
Table 19-13: <br />
(CHNL_PRIORITY_SET, 0x4004 C038) <br />
<br />
27:0 CHNL_PRIORITY_SET <br />
0x0<br />
<br />
[c] = 0DMA c <br />
[c] = 1DMA c <br />
<br />
[c] = 0<br />
CHNL_PRIORITY_CLR <br />
c <br />
[c] = 1 c <br />
31:28 - . NA<br />
19.6.3 <br />
<br />
DMA c (c = 0-27) <br />
272 www.xinnovatech.com
XN62Lxxx<br />
Table 19-14: <br />
(CHNL_PRIORITY_CLR, 0x4004 C03C) <br />
<br />
27:0 CHNL_PRIORITY_CLR <br />
DMA -<br />
<br />
[c] = 0<br />
CHNL_PRIORITY_SET <br />
c <br />
[c] = 1 c <br />
31:28 - . NA<br />
19.6.4 DMA <br />
/<br />
<br />
DMA c (c = 0-27) DMA “1”<br />
Table 19-15: DMA <br />
(CHNL_IRQ_STATUS, 0x4004 C080) <br />
Reset <br />
27:0 CHNL_IRQ_STAT <br />
DMA <br />
0x0<br />
<br />
[c] = 0DMA <br />
[c] = 1 c DMA <br />
<br />
[c] = 0<br />
[c] = 1 c DMA <br />
31:28 - . NA<br />
19.6.5 DMA <br />
/<br />
<br />
DMA c (c = 0-27) DMA <br />
Table 19-16: DMA <br />
(CHNL_IRQ_ENABLE, 0x4004 C088) <br />
<br />
27:0 CHNL_IRQ_ENABLE DMA (dma_done[c]) <br />
0x0<br />
<br />
[c] = 0 c DMA <br />
[c] = 1 c DMA <br />
31:28 - . NA<br />
19.7 <br />
19.7.1 DMA <br />
<br />
DMA <br />
DMA www.xinnovatech.com 273
XN62Lxxx<br />
Table 19-17: DMA <br />
/ <br />
<br />
DMA dma_req[c]<br />
<br />
/<br />
<br />
<br />
dma_req[c] 2 R DMA DMA <br />
R_power <br />
<br />
c dma_req[c] <br />
<br />
DMA<br />
dma_sreq[c]<br />
/<br />
<br />
dma_sreq <br />
<br />
DMA DMA <br />
c dma_sreq[c] <br />
<br />
19.7.2 DMA<br />
<br />
DMA <br />
<br />
AHB R_power R 2 <br />
R = 4<br />
24<br />
16 DMA <br />
<br />
R_power <br />
N > 2 R<br />
2 R <br />
2 R <br />
N
XN62Lxxx<br />
... ...<br />
27 <br />
19.7.4 DMA<br />
<br />
cycle_ctrl DMA <br />
<br />
• <br />
• <br />
• <br />
<br />
2 R DMA <br />
2 R DMA <br />
DMA <br />
channel_cfg <br />
R_power <br />
<br />
<br />
DMA DMA<br />
<br />
<br />
1. 2 R <br />
0<br />
3 2. <br />
a) <br />
b) <br />
1 3. <br />
dma_done[c] <br />
DMA <br />
<br />
1. 2 R <br />
0<br />
3 2. 2 R <br />
c 1 3. <br />
dma_done[c] <br />
DMA 19.7.5 DMA<br />
SRAM <br />
DMA DMA<br />
SRAM <br />
www.xinnovatech.com 275
XN62Lxxx<br />
1024 <br />
28 28 <br />
<br />
SRAM <br />
0x1000 0000 0x1000 3F00 <br />
CTRL_BASE_PTR <br />
DMA (SRAM)<br />
1GB<br />
alternate channel 20<br />
.<br />
.<br />
.<br />
alternate channel 1<br />
alternate channel 0<br />
primary channel 20<br />
.<br />
.<br />
.<br />
primary channel 1<br />
primary channel 0<br />
0x2A0<br />
0x2B0<br />
0x170<br />
0x160<br />
0x150<br />
0x140<br />
0x020<br />
0x010<br />
0x000<br />
unused<br />
channel control data<br />
destination end pointer<br />
source end pointer<br />
0x00C<br />
0x008<br />
0x004<br />
0x000<br />
Figure 19-2: DMA <br />
19.7.5.1 <br />
src_data_end_ptr <br />
DMA <br />
2 R DMA <br />
DMA <br />
<br />
<br />
Table 19-19: src_data_end_ptr <br />
<br />
31:0 src_data_end_ptr <br />
19.7.5.2 <br />
dst_data_end_ptr <br />
DMA<br />
2<br />
R DMA <br />
<br />
<br />
Table 19-20: dst_data_end_ptr <br />
<br />
31:0 dst_data_end_ptr <br />
276 www.xinnovatech.com
XN62Lxxx<br />
19.7.5.3 <br />
DMA channel_cfg DMA<br />
2<br />
<br />
SRAM channel_cfg<br />
<br />
2 R N <br />
channel_cfg SRAM <br />
src_size<br />
dst_size <br />
n_minus_1 dst_size<br />
src_size N<br />
cycle_ctrl<br />
000 channel_cfg SRAM<br />
<br />
R<br />
SRAM<br />
.<br />
Table 19-21: channel_cfg <br />
Name <br />
2:0 cycle_ctrl DMA <br />
3 <br />
000: <br />
001: /<br />
DMA 100 - 111<br />
13:4 n_minus_1 DMA <br />
DMA DMA <br />
DMA <br />
10 DMA <br />
000000000 = 1 DMA <br />
000000001 = 2 DMA <br />
000000010 = 3 DMA <br />
000000011 = 4 DMA <br />
000000100 = 5 DMA <br />
...<br />
111111111 = 1024 DMA <br />
<br />
DMA DMA <br />
17:14 R_power <br />
DMA <br />
0000: DMA <br />
0001: 2 DMA <br />
0010: 4 DMA <br />
0011: 8 DMA <br />
0100: 16 DMA <br />
0101: 32 DMA <br />
0110: 64 DMA <br />
0111: 128 DMA <br />
1000: 256 DMA <br />
1001: 512 DMA <br />
www.xinnovatech.com 277
XN62Lxxx<br />
23:18 - -<br />
1010-1111: 1024 DMA <br />
DMA <br />
1024<br />
25:24 src_size <br />
00 = <br />
01 = <br />
10 = <br />
11 = <br />
27:26 src_inc <br />
=<br />
00 = .<br />
01 = .<br />
10 = .<br />
11 =<br />
src_data_end_ptr <br />
=<br />
00 = .<br />
01 = .<br />
10 = .<br />
11 =<br />
src_data_end_ptr <br />
=<br />
00 = .<br />
01 = .<br />
10 = .<br />
11 =<br />
src_data_end_ptr <br />
29:28 dst_size <br />
00 = <br />
01 = <br />
10 = <br />
11 = <br />
31:30 dst_inc <br />
<br />
=<br />
00 = .<br />
01 = .<br />
10 = .<br />
11 =<br />
dst_data_end_ptr <br />
=<br />
00 = .<br />
01 = .<br />
10 = .<br />
11 =<br />
dst_data_end_ptr <br />
=<br />
278 www.xinnovatech.com
XN62Lxxx<br />
00 = .<br />
01 = .<br />
10 = .<br />
11 =<br />
dst_data_end_ptr <br />
www.xinnovatech.com 279
XN62Lxxx<br />
20 Flash/SRAM ISP/IAP <br />
XN62 88 KB Flash 16 KB SRAM <br />
Flash <br />
(ISP)<br />
(IAP)<br />
<br />
XN62L bootloader ISP/IAP XN62L 128 <br />
A/B <br />
20.1 Flash/Boot ROM <br />
XN62L Flash 1K <br />
88 Flash <br />
0 <br />
ROM 8KB <br />
MCU bootloaderboot loader 0x1FFF0000<br />
Reserved<br />
0x1FFF 2000<br />
0x1FFF 0000<br />
Boot Loader<br />
Reserved<br />
0x0001 6000<br />
0x0001 5FFF<br />
0x0001 5C00<br />
Sector 87<br />
User App.<br />
0x0000 0800<br />
0x0000 0400<br />
0x0000 0000<br />
Sector 1<br />
Sector 0<br />
Figure 20-1:<br />
Flash <br />
XN62L (MAM<br />
) 64 Flash IPFlash <br />
<br />
280 www.xinnovatech.com
XN62Lxxx<br />
Flash Control<br />
Address<br />
Address<br />
M0 Core<br />
32bits Data Bus<br />
MAM<br />
64bits Data Bus<br />
On Chip Flash<br />
Rdy/Bsy<br />
Figure 20-2: <br />
(MAM) 20.2 Flash /<br />
Table 20-1: Flash <br />
(: 0x5006 0000)<br />
· <br />
~ 0x00~0x24 ~ <br />
FLASH_RDCYC 0x28 R/W Flash 0x0000 0000<br />
DID 0x2C RO ID<br />
0xxxxx xxxx<br />
VERID 0x30 RO 0xxxxx xxxx<br />
UNIQUEID 0x34 RO 0xxxxx xxxx<br />
20.2.1 Flash <br />
Flash<br />
FLASH_RDCYC <br />
Table 20-2: Flash <br />
(FLASH_RDCYC, 0x5006 0028) <br />
<br />
1:0 CYCLES Flash 00<br />
00 1 <br />
system clock 30MHz <br />
01 2 <br />
system clock 60MHz <br />
10 3 <br />
system clock 60MHz 90MHz<br />
<br />
11 4 <br />
system clock 90MHz <br />
31:2 - - - 0x0<br />
20.2.2 ID<br />
Table 20-3: ID (DID, 0x5006 002C) <br />
<br />
15:0 DID ID<br />
31:16 MID <br />
ID<br />
XXXX<br />
XXXX<br />
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XN62Lxxx<br />
20.2.3 <br />
Table 20-4: <br />
(VERID, 0x5006 0030) <br />
<br />
15:0 MINOR XXXX<br />
31:16 MAJOR XXXX<br />
20.2.4 <br />
Table 20-5: <br />
(UNIQUEID, 0x5006 0034) <br />
<br />
31:0 SID XXXXXXXX<br />
20.3 Flash<br />
XN62L 128 <br />
Flash Fl<br />
SRAM <br />
0x0001 5FFF<br />
Flash Memory(88KB)<br />
0x10003000<br />
SRAM(16KB)<br />
Access Control by<br />
B Area<br />
B Area<br />
Password B (128 bits)<br />
0x000x xxxx<br />
0x1000 xxxx<br />
Open Area<br />
A Area<br />
0x1000 0000<br />
Password A (128 bits)<br />
0x0000 0000<br />
Figure 20-3: / <br />
Figure 20-3 128 <br />
SWD<br />
A B <br />
1. B <br />
A/B/<br />
B SRAM <br />
2. A <br />
B <br />
B 3. A <br />
A <br />
4. Flash<br />
<br />
5. SWD <br />
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XN62Lxxx<br />
20.3.1 A/B<br />
<br />
Flash SRAM A,B <br />
A,B <br />
Flash A <br />
A <br />
Flash/SRAM B <br />
ISP/IAP B <br />
<br />
ISP/IAP : SRAM 2K Flash<br />
<br />
20.3.2 <br />
/<br />
()<br />
20.3.3 <br />
Table 20-6: A <br />
<br />
<br />
<br />
B/A/<br />
ISP A SWD A <br />
DMA A <br />
<br />
<br />
<br />
Flash / B/A/<br />
ISP A <br />
SRAM <br />
<br />
SWD A <br />
A <br />
<br />
<br />
Table 20-7: B <br />
<br />
<br />
<br />
B <br />
B A <br />
B SWD B <br />
ISP B <br />
DMA B <br />
<br />
<br />
<br />
<br />
<br />
Flash / B/A/<br />
ISP B <br />
SRAM <br />
<br />
B <br />
B SRAM<br />
SWD B <br />
DMA B SRAM<br />
B <br />
<br />
<br />
<br />
<br />
20.4 ISP <br />
ISP <br />
XN MCU UART0 .<br />
• UART 1<br />
, 8, , 1 <br />
ISP <br />
:<br />
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XN62Lxxx<br />
<br />
(2 0x55AA)<br />
<br />
<br />
( ) CRC16<br />
(1 ) (1 ) (1 ) (1 ) (2 )<br />
:<br />
( ) CRC16<br />
Figure 20-4: ISP <br />
• : ,<br />
: 0x55AA<br />
• : <br />
CRC<br />
• : - ; 1 - . 0<br />
• : .<br />
• :<br />
0, <br />
0 <br />
• : .<br />
• / : .<br />
• CRC: 2 CRC16(:0xFFFF) .<br />
20.4.1 ISP <br />
ISP :<br />
ISP<br />
4 <br />
4 <br />
• <br />
#01H<br />
• #03H<br />
• #04H<br />
Table 20-8: ISP <br />
<br />
<br />
#01H #11H 2 8 No<br />
#02H #12H 2 8 No<br />
SRAM #04H #14H 2 8 Yes<br />
SRAM Flash #05H #15H 3 12 No<br />
#06H #16H 3 12 No<br />
#07H #17H 2 8 No<br />
#08H #18H 0 0 No<br />
<br />
ID #01H #31H 0 0 No<br />
Bootloader #02H #32H 0 0 No<br />
<br />
<br />
#02H #42H 0 0 No<br />
#0AH #4AH 1 16 No<br />
#0BH #4BH 2 32 No<br />
B #0CH #4CH 2 20 No<br />
20.4.2 ISP<br />
ISP ISP<br />
<br />
284 www.xinnovatech.com
XN62Lxxx<br />
: #08H<br />
: #09H<br />
: #0AH<br />
: #0BH<br />
Table 20-9: ISP <br />
<br />
<br />
#11H #11H 0 0 No<br />
#12H #12H 0 0 No<br />
SRAM #14H #14H 0 0 No<br />
<br />
SRAM Flash #15H #15H 0 0 No<br />
#16H #16H 0 0 No<br />
#17H #17H No<br />
#18H #18H 0 0 No<br />
<br />
ID #31H #31H 3 12 No<br />
Bootloader #32H #32H 2 8 No<br />
#42H #42H 0 0 No<br />
#4AH #4AH 0 0 No<br />
#4BH #4BH 0 0 No<br />
B #4CH #4CH 0 0 No<br />
Table 20-10: ISP <br />
<br />
<br />
#01H #81H 0 0 No<br />
#02H #82H 0 0 No<br />
#03H #83H 0 0 No<br />
CRC #04H #84H 0 0 No<br />
#01H #91H 0 0 No<br />
Flash #02H #92H 0 0 No<br />
Flash #03H #93H 1 4 No<br />
1 #01H #A1H 0 0 No<br />
2 #02H #A2H 0 0 No<br />
3 #03H #A3H 0 0 No<br />
#01H #B1H 0 0 No<br />
20.4.3 <br />
: 0x11H<br />
:<br />
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XN62Lxxx<br />
<br />
<br />
– : 0~ Flash flash <br />
– :<br />
<br />
~ flash <br />
: 0x11H<br />
:<br />
<br />
20.4.4 <br />
: 0x12H<br />
:<br />
<br />
– : Flash 0 ~ Flash <br />
– : ~<br />
Flash <br />
: 0x12H<br />
:<br />
<br />
20.4.5 SRAM<br />
1.: 0x14H<br />
:<br />
<br />
– : SRAM =0x10 000400<br />
– : 0~1024<br />
2.MCU :<br />
0x14H xFF <br />
3. <br />
<br />
4.MCU : <br />
0x14Hx00 <br />
20.4.6 RAM Flash<br />
: 0x15H<br />
:<br />
Flash (32 ) SRAM (32 ) (32 )<br />
– Flash : Flash <br />
– SRAM : SRAM =0x10000400<br />
– : Flash <br />
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XN62Lxxx<br />
: 0x15H<br />
:<br />
<br />
20.4.7 <br />
: 0x16H<br />
:<br />
(32 ) (32 ) (32<br />
)<br />
– <br />
– <br />
– <br />
: 0x16H<br />
:<br />
<br />
20.4.8 <br />
: 0x17H<br />
:<br />
(32 ) (32<br />
)<br />
– : <br />
– : <br />
: 0x17H<br />
:<br />
<br />
– : MCU <br />
20.4.9 <br />
: 0x18H<br />
: 0x18H<br />
<br />
20.4.10 ID<br />
: 0x31H<br />
: 0x31H<br />
:<br />
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XN62Lxxx<br />
ID(32 ) (32 s) (32<br />
) Flash (32 ) SRAM (32 )<br />
– ID: 16 ID + 16 ID<br />
– : <br />
– .: 32<br />
– Flash : <br />
– SRAM : <br />
20.4.11 BSL<br />
: 0x32H<br />
: 0x32H<br />
(16 ) (16 ) (32 )<br />
: 1~255<br />
:1~255<br />
:<br />
20.4.12 <br />
: 0x42H<br />
<br />
– : Flash RAM <br />
– : 0: Flash; loader 1: Boot<br />
: 0x42H<br />
20.4.13 <br />
: 0x4AH<br />
:<br />
AB (32 ) (128 )<br />
– AB 0: A; 1: B.<br />
– : <br />
128<br />
: 0x4AH<br />
:<br />
AB (32 )<br />
20.4.14 <br />
: 0x4BH<br />
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XN62Lxxx<br />
:<br />
AB (32 ) (128 ) (128 )<br />
– AB 0: A; 1: B.<br />
– : 128<br />
– : 128<br />
: 0x4BH<br />
:<br />
AB (32 )<br />
20.4.15 B<br />
: 0x4CH<br />
:<br />
AB (32 ) 128 Flash (32 ) SRAM (32 )<br />
– AB : 1<br />
– : <br />
128<br />
– Flash : <br />
32<br />
– SRAM : <br />
32<br />
: 0x4CH<br />
:<br />
AB (32 )<br />
20.4.16 <br />
: 0x4DH<br />
: 0x4DH<br />
:<br />
A (32 ) B (32 ) B Flash (32 ) B SRAM (32 )<br />
– A 0: ; 0: <br />
– B 0: ; 0: <br />
– Flash : <br />
32<br />
– SRAM : <br />
32<br />
20.5 IAP<br />
BSL IAP Thumb <br />
0x1FFF 1FF0 <br />
r0 <br />
IAP (RAM)<br />
IAP r1 www.xinnovatech.com 289
XN62Lxxx<br />
<br />
r0 r1 <br />
<br />
IAP COMMAND CODE<br />
PARAMETER 1<br />
command<br />
parameter table<br />
PARAMETER 2<br />
ARM REGISTER r0<br />
ARM REGISTER r1<br />
PARAMETER n<br />
STATUS CODE<br />
RESULT 1<br />
command<br />
result table<br />
RESULT 2<br />
RESULT n<br />
Figure 20-5: IAP <br />
<br />
C IAP <br />
IAP <br />
IAP 0 <br />
Thumb<br />
<br />
#define IAP_LOCATION 0x1fff1001<br />
<br />
IAP <br />
IAP :<br />
unsigned long command[10];<br />
unsigned long result[5];<br />
<br />
unsigned long * command;<br />
unsigned long * result;<br />
command=(unsigned long *) 0x……<br />
result= (unsigned long *) 0x……<br />
<br />
2 <br />
IAP R1 <br />
typedef void (*IAP)(unsigned int [],unsigned int[]);<br />
IAP iap_entry;<br />
<br />
iap_entry=(IAP) IAP_LOCATION;<br />
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XN62Lxxx<br />
<br />
IAP<br />
iap_entry (command, result);<br />
Table 20-11: IAP <br />
IAP <br />
R0 <br />
R1 <br />
<br />
1 2 3~6 5~9 <br />
<br />
1 2 3 4<br />
BSL 0x31 - - - - Major&<br />
- -<br />
Minor<br />
0x11<br />
- - - - - - -<br />
0x15 - - - - - -<br />
0x4A A/B 128 - - - - -<br />
0x4B A/B 128 128 - - - -<br />
B 0x4C A/B 128 B Flash SRAM <br />
- -<br />
<br />
<br />
0x4D<br />
<br />
A B B Flash<br />
B SRAM<br />
<br />
<br />
<br />
<br />
IAP :<br />
1. CMD_SUCC 0x00<br />
2. INVALID_ADDR 0x01<br />
3. ERASE_FAILED 0x02<br />
4. PROG_FAILED 0x03<br />
5. NOT_BLANK 0x04<br />
6. INVALID_CMD 0x05<br />
7. INVALID_PWD 0x06<br />
8. IRC_NOT_POWERED 0x07<br />
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XN62Lxxx<br />
21 SWD<br />
21.1 <br />
XN62L SWD <br />
ARM Serial Wire Debug mode<br />
• <br />
• <br />
• 4 4 <br />
2 • 2 <br />
21.2 <br />
Table 21-1: SWD <br />
<br />
SWCLK (SW<br />
SWDIO<br />
/ <br />
<br />
/ <br />
SWDIO ARM Cortex-M0 CPU<br />
<br />
21.3 <br />
SWD <br />
SWD SWD <br />
SWD A <br />
SWD <br />
SWD <br />
XN62Lxxx<br />
signals from SWD connector<br />
SWDIO<br />
SWCLK<br />
nSRST<br />
GND<br />
Gnd<br />
SWDIO<br />
SWCLK<br />
RESET#<br />
PIO0_12<br />
ISP entry<br />
Figure 21-1: SWD SWD <br />
292 www.xinnovatech.com
XN62Lxxx<br />
22 <br />
<br />
1.0 Initial Release. May 2012<br />
1.1 Revised ADC, ISP/IAP sections. Aug. 2012<br />
1.2 Document Revision Apr. 2013<br />
1.3 Revised power down wakeup May 2013<br />
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