TESTtz

ACS712
Fully Integrated, Hall Effect-Based Linear Current Sensor with
2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor
Chopper Stabilization Technique
Chopper Stabilization is an innovative circuit technique that is
used to minimize the offset voltage of a Hall element and an associated
on-chip amplifier. Allegro patented a Chopper Stabilization
technique that nearly eliminates Hall IC output drift induced
by temperature or package stress effects. This offset reduction
technique is based on a signal modulation-demodulation process.
Modulation is used to separate the undesired dc offset signal from
the magnetically induced signal in the frequency domain. Then,
using a low-pass filter, the modulated dc offset is suppressed
while the magnetically induced signal passes through the filter.
As a result of this chopper stabilization approach, the output
voltage from the Hall IC is desensitized to the effects of temperature
and mechanical stress. This technique produces devices that
have an extremely stable Electrical Offset Voltage, are immune to
thermal stress, and have precise recoverability after temperature
cycling.
This technique is made possible through the use of a BiCMOS
process that allows the use of low-offset and low-noise amplifiers
in combination with high-density logic integration and sample
and hold circuits.
Hall Element
Regulator
Clock/Logic
Amp
Sample and
Hold
Concept of Chopper Stabilization Technique
Low-Pass
Filter
Typical Applications
+5 V
V PEAK
+5 V
I P
C BYP
0.1 µF
1
IP+
2
IP+
8
VCC
7
VIOUT
ACS712
3
6
IP–
FILTER
4
IP– 5
GND
R F
10 kΩ
+5 V
8
1
IP+
VCC
2
7
IP+ VIOUT
I P ACS712
3 6
IP–
FILTER
4
IP– 5
GND
C OUT
0.1 µF
V OUT
R1
1 MΩ
C F
1 nF
R2
33 kΩ
Application 2. Peak Detecting Circuit
C BYP
0.1 µF
R F
2 kΩ
V OUT
+
–
R1
10 kΩ
C F
1 nF
R3
330 kΩ
C2
0.1 µF
R4
10 kΩ
U1
LT1178
D1
1N4448W
C1
D1
1N914
C1
0.1 µF
V RESET
Q1
2N7002
A-to-D
Converter
Application 4. Rectified Output. 3.3 V scaling and rectification application
for A-to-D converters. Replaces current transformer solutions with simpler
ACS circuit. C1 is a function of the load resistance and filtering desired.
R1 can be omitted if the full range is desired.
C BYP
0.1 µF
R2
+
100 kΩ
1 LM321
8
5
1
IP+
VCC
4
2
7
– 3
IP+ VIOUT
2
R F
I P ACS712
1 kΩ
3
6
R3
IP–
FILTER
3.3 kΩ
C F
4
IP– 5
0.01 µF
GND
C BYP
0.1 µF
+5 V
R1
100 kΩ
8
1
IP+
VCC
2
7
IP+ VIOUT
I P ACS712
3
6
IP–
FILTER
4
IP– 5
GND
R1
33 kΩ
R2
100 kΩ
V OUT
C F
1 nF
4
–
3 +
5
2
1
U1
LMV7235
D1
1N914
V OUT
C1
1000 pF
Application 3. This configuration increases gain to 610 mV/A
(tested using the ACS712ELC-05A).
R PU
100 kΩ
Application 5. 10 A Overcurrent Fault Latch. Fault threshold set by R1 and
R2. This circuit latches an overcurrent fault and holds it until the 5 V rail is
powered down.
Fault
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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