Modulação Vetorial Aplicada ao Retificador Trifásico PWM - Ivo Barbi
Modulação Vetorial Aplicada ao Retificador Trifásico PWM - Ivo Barbi Modulação Vetorial Aplicada ao Retificador Trifásico PWM - Ivo Barbi
265LDP #VorefSPLK #22012, VorefLDP #VorefnomSPLK #28768, VorefnomLDP #VmedioSPLK #24658, VmedioLDP #VminSPLK #18986, VminLDP #Vmin1SPLK #17437, Vmin1LDP #histereseSPLK #0, histereseLDP #VmaxSPLK #32056, VmaxLDP #Vmax1SPLK #30822, Vmax1LDP #histerese2SPLK #0, histerese2LDP #fatorSPLK #1,fatorLDP #IDrefFSPLK #0, IDrefFLDP #IDrefFANTSPLK #0, IDrefFANTLDP #K1ISPLK #19939, K1ILDP #K2ISPLK #8323, K2ILDP #K1FSPLK #27099, K1FLDP #K2FSPLK #5669, K2FLDP #K1VSPLK #29196, K1VLDP #K2VSPLK #21561, K2VLDP #KARWVSPLK #16384, KARWVLDP #KARWISPLK #3277, KARWILDP #IDrefSATANTSPLK #0, IDrefSATANTLDP #DqlinhaSATSPLK #0, DqlinhaSATLDP #UmquartoSPLK #8193,UmquartoLDP #temporizadorSPLK #0,temporizadorLDP #soma_ASPLK #0, soma_ALDP #media_ASPLK #16384, media_ALDP #soma_BSPLK #0, soma_BLDP #media_BSPLK #16384, media_BLDP #soma_CSPLK #0, soma_CLDP #media_CSPLK #16384, media_CLDP #soma_VOSPLK #0, soma_VOLDP #VomedSPLK #0, VomedLDP #KmedSPLK #195,KmedLDP #InibeSPLK #666, InibeLDP #TABELALAR AR5, #TABELALAR AR6, #1hLAR AR7, #(TABELA+126);~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Desabilita o watchdog;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF1SPLK #11101000b, WDCR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os regs. de controle do sist.;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF1SPLK #0000000011111101b, SCSR1SPLK #0000000000001111b, SCSR2;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura a pilha;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LAR AR1, #stkMAR *, AR1;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura as interrupcoes do nucleo;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #0hSPLK #111111b,IFRSPLK #000001b,IMR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos de I/O;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2SPLK #0000000000000000b,MCRASPLK #1111111000000000b,MCRBSPLK #0000000000101010b,MCRC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos do IOPA como saida;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PADATDIROR #1111111100000000bSACL PADATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos do IOPB como saida;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PBDATDIROR #1111111100000000bSACL PBDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos do IOPC como saida;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PCDATDIROR #1111111100000000bSACL PCDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura pino IOPE7 como saída;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PEDATDIROR #1000000010000000bSACL PEDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura pinos IOPF 0-6 como entrada;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PFDATDIRAND #1000000011111111bSACL PFDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura o ADC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2SPLK #0100000000000000b, ADCTRL1SPLK #0000000000000011b,MAX_CONVSPLK #0011001000010000b,CHSELSEQ1SPLK #0010000000010000b, ADCTRL1SPLK #1100011000000010b, ADCTRL2;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Config. Full Compare 4,5 e 6 e GP Timer 3;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
266LDP #DP_EVBSPLK #0000h, T3CONSPLK #0000h, T3CNTSPLK #pwm_half_per, T3PRSPLK #0000h, DBTCONBSPLK #0, CMPR4SPLK #0, CMPR5SPLK #0, CMPR6SPLK #0000000010000000b, GPTCONBSPLK #0000000100010001b, ACTRBSPLK #1010001000000000b, COMCONBSPLK #1000100001000100b, T3CON;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura as interrupcoes dos EVMs;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_EVASPLK #0FFFFh, EVAIFRASPLK #0FFFFh, EVAIFRBSPLK #0FFFFh, EVAIFRCSPLK #00000h, EVAIMRASPLK #00000h, EVAIMRBSPLK #00000h, EVAIMRCLDP #DP_EVBSPLK #0FFFFh, EVBIFRASPLK #0FFFFh, EVBIFRBSPLK #0FFFFh, EVBIFRCSPLK #00000h, EVBIMRASPLK #00000h, EVBIMRBSPLK #00000h, EVBIMRC; atualiza os PWMs DA, DB e DC =0LDP #DALACC DALDP #DP_EVBSACL CMPR4LDP #DBLACC DBLDP #DP_EVBSACL CMPR5LDP #DCLACC DCLDP #DP_EVBSACL CMPR6;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Habilita interrupcoes globais;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~CLRC INTM;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Laco principal;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Loop: NOPB loop;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Rotina de tratamneto da interrupcao ADC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~adc_isr:;salva contextoMAR *,AR1MAR *+SST #1, *+SST #0, *+SACH *+SACL *+SAR AR2, *+SAR AR0, *+SAR AR3, *+SAR AR4, *+;limpa o INT_FLAG_SEQ1 e le o ADCCLR CSXMLDP #DP_PF2LACC ADCTRL2SACL ADCTRL2;armazena variáveis lidas no ADLACC #0LDP #DP_PF2LACC RESULT3,15LDP #VOSACH VOLACC #0LDP #DP_PF2LACC RESULT2,15LDP #ICSACH ICLACC #0LDP #DP_PF2LACC RESULT1,15LDP #IBSACH IBLACC #0LDP #DP_PF2LACC RESULT0,15LDP #IASACH IA;reset ADC SEQ1 para o estado CONV00LDP #DP_PF2LACC ADCTRL2OR #4000hSACL ADCTRL2;media da tensao de saidaSETC SXMSETC OVMSPM 1LACC #0MPY #0LDP #VOLT VOLDP #KmedMPY KmedAPACLDP #soma_VOADD soma_VO,16SACH soma_VO; partida suave de tensaoLDP #VorefLACC VorefADD #1SACL VorefMAR *,AR4LAR AR4,VorefLDP #VorefnomLAR AR0,VorefnomCMPR 2BCND nlimita, NTCLACC VorefnomLDP #VorefSACL Vorefnlimita:;proteção de tensão minima na malha VMAR *,AR4LDP #VOLAR AR4,VOLDP #VminLAR AR0,VminCMPR 1BCND nreiniciamv, NTCLACC #0LDP #VOLACC VOLDP #VorefSACL VorefLDP #IDLACC IDLDP #IDrefIANTSACL IDrefIANTLDP #IDrefFANTSACL IDrefFANTLDP #IDrefSATANTSACL IDrefSATANTnreiniciamv:;teste de sincronismo - passagem por zero
- Page 229 and 230: 214Neste caso, observa-se que as fo
- Page 231 and 232: 216Estas grandezas apresentam forma
- Page 233 and 234: 218VS( t)iS( t )V ( t)D1iD1( t )a)
- Page 235 and 236: 2208.5.2. Operação com V L = 380
- Page 237 and 238: 222Tabela 8-7 - Fator de potência.
- Page 239 and 240: 224Na Fig. 8-41, na Fig. 8-42 e na
- Page 241 and 242: 226CONCLUSÃO GERALForam demonstrad
- Page 243 and 244: 228dos valores teóricos, validando
- Page 245 and 246: 230R83C386.94kV15n714nVo5/400R82 TL
- Page 247 and 248: 232V_V46 V15n 0 DC -15D_D43 $N_0005
- Page 249 and 250: I234ANEXO B. Diagrama Esquemático
- Page 251 and 252: 236um5um1Eq1um1Eq4Dalfa1.225Dalfa1.
- Page 253 and 254: 238.ends qualyuniy20k_S36.subckt qu
- Page 255 and 256: 240R97C497.7kV15n646nVo5/400R92 TL0
- Page 257 and 258: 242E_SUM26 $N_0009 0 VALUE{V($N_001
- Page 259 and 260: 244ANEXO D. Dimensionamento do Est
- Page 261 and 262: 246D.2. Dimensionamento dos Indutor
- Page 263 and 264: 248⎧ vA(t) + vB(t) + vC(t) = 0⎪
- Page 265 and 266: 250P 0,613⋅V −2⋅η⋅VI = ⋅
- Page 267 and 268: 252ππ⎧⎫6 61 ⎪⎪IS = ⋅⎨
- Page 269 and 270: 254ID3456MEDdiodos D I3456 .0⎧⎫
- Page 271 and 272: 256ANEXO E. Esquemas Elétricos das
- Page 273 and 274: 258C7100pF1110U2ALF347324111+-V+V-O
- Page 275 and 276: 260GNDVsincA10k56nR54C31+15VR473.3k
- Page 277 and 278: 262Barra de PinosBarra de Pinos1Bar
- Page 279: 264int10: B int10int11: B int11int1
- Page 283 and 284: 268SACL IDrefSATMAR *,AR4LDP #IDref
- Page 285 and 286: 270; Dqlinha (total)LDP #DqlinhaPAD
- Page 287 and 288: 272LDP #KD_1LT KD_1MPY DalfaSPACLDP
- Page 289 and 290: 274CLRC SXMCLRC OVM; testa Inibe pa
- Page 291 and 292: 276REFERÊNCIAS BIBLIOGRÁFICAS[1]
- Page 293 and 294: 278[21] AREDES, M.; Active Power Li
- Page 295 and 296: 280[44] BOTTERÓN, F.; Análise, Pr
- Page 297: 282[67] BORGONOVO, Deivis; Análise
266LDP #DP_EVBSPLK #0000h, T3CONSPLK #0000h, T3CNTSPLK #pwm_half_per, T3PRSPLK #0000h, DBTCONBSPLK #0, CMPR4SPLK #0, CMPR5SPLK #0, CMPR6SPLK #0000000010000000b, GPTCONBSPLK #0000000100010001b, ACTRBSPLK #1010001000000000b, COMCONBSPLK #1000100001000100b, T3CON;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura as interrupcoes dos EVMs;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_EVASPLK #0FFFFh, EVAIFRASPLK #0FFFFh, EVAIFRBSPLK #0FFFFh, EVAIFRCSPLK #00000h, EVAIMRASPLK #00000h, EVAIMRBSPLK #00000h, EVAIMRCLDP #DP_EVBSPLK #0FFFFh, EVBIFRASPLK #0FFFFh, EVBIFRBSPLK #0FFFFh, EVBIFRCSPLK #00000h, EVBIMRASPLK #00000h, EVBIMRBSPLK #00000h, EVBIMRC; atualiza os <strong>PWM</strong>s DA, DB e DC =0LDP #DALACC DALDP #DP_EVBSACL CMPR4LDP #DBLACC DBLDP #DP_EVBSACL CMPR5LDP #DCLACC DCLDP #DP_EVBSACL CMPR6;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Habilita interrupcoes globais;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~CLRC INTM;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Laco principal;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Loop: NOPB loop;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Rotina de tratamneto da interrupc<strong>ao</strong> ADC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~adc_isr:;salva contextoMAR *,AR1MAR *+SST #1, *+SST #0, *+SACH *+SACL *+SAR AR2, *+SAR AR0, *+SAR AR3, *+SAR AR4, *+;limpa o INT_FLAG_SEQ1 e le o ADCCLR CSXMLDP #DP_PF2LACC ADCTRL2SACL ADCTRL2;armazena variáveis lidas no ADLACC #0LDP #DP_PF2LACC RESULT3,15LDP #VOSACH VOLACC #0LDP #DP_PF2LACC RESULT2,15LDP #ICSACH ICLACC #0LDP #DP_PF2LACC RESULT1,15LDP #IBSACH IBLACC #0LDP #DP_PF2LACC RESULT0,15LDP #IASACH IA;reset ADC SEQ1 para o estado CONV00LDP #DP_PF2LACC ADCTRL2OR #4000hSACL ADCTRL2;media da tens<strong>ao</strong> de saidaSETC SXMSETC OVMSPM 1LACC #0MPY #0LDP #VOLT VOLDP #KmedMPY KmedAPACLDP #soma_VOADD soma_VO,16SACH soma_VO; partida suave de tens<strong>ao</strong>LDP #VorefLACC VorefADD #1SACL VorefMAR *,AR4LAR AR4,VorefLDP #VorefnomLAR AR0,VorefnomCMPR 2BCND nlimita, NTCLACC VorefnomLDP #VorefSACL Vorefnlimita:;proteção de tensão minima na malha VMAR *,AR4LDP #VOLAR AR4,VOLDP #VminLAR AR0,VminCMPR 1BCND nreiniciamv, NTCLACC #0LDP #VOLACC VOLDP #VorefSACL VorefLDP #IDLACC IDLDP #IDrefIANTSACL IDrefIANTLDP #IDrefFANTSACL IDrefFANTLDP #IDrefSATANTSACL IDrefSATANTnreiniciamv:;teste de sincronismo - passagem por zero
Change language