ModulaÃ§Ã£o Vetorial Aplicada ao Retificador TrifÃ¡sico PWM - Ivo Barbi

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265LDP #VorefSPLK #22012, VorefLDP #VorefnomSPLK #28768, VorefnomLDP #VmedioSPLK #24658, VmedioLDP #VminSPLK #18986, VminLDP #Vmin1SPLK #17437, Vmin1LDP #histereseSPLK #0, histereseLDP #VmaxSPLK #32056, VmaxLDP #Vmax1SPLK #30822, Vmax1LDP #histerese2SPLK #0, histerese2LDP #fatorSPLK #1,fatorLDP #IDrefFSPLK #0, IDrefFLDP #IDrefFANTSPLK #0, IDrefFANTLDP #K1ISPLK #19939, K1ILDP #K2ISPLK #8323, K2ILDP #K1FSPLK #27099, K1FLDP #K2FSPLK #5669, K2FLDP #K1VSPLK #29196, K1VLDP #K2VSPLK #21561, K2VLDP #KARWVSPLK #16384, KARWVLDP #KARWISPLK #3277, KARWILDP #IDrefSATANTSPLK #0, IDrefSATANTLDP #DqlinhaSATSPLK #0, DqlinhaSATLDP #UmquartoSPLK #8193,UmquartoLDP #temporizadorSPLK #0,temporizadorLDP #soma_ASPLK #0, soma_ALDP #media_ASPLK #16384, media_ALDP #soma_BSPLK #0, soma_BLDP #media_BSPLK #16384, media_BLDP #soma_CSPLK #0, soma_CLDP #media_CSPLK #16384, media_CLDP #soma_VOSPLK #0, soma_VOLDP #VomedSPLK #0, VomedLDP #KmedSPLK #195,KmedLDP #InibeSPLK #666, InibeLDP #TABELALAR AR5, #TABELALAR AR6, #1hLAR AR7, #(TABELA+126);~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Desabilita o watchdog;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF1SPLK #11101000b, WDCR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os regs. de controle do sist.;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF1SPLK #0000000011111101b, SCSR1SPLK #0000000000001111b, SCSR2;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura a pilha;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LAR AR1, #stkMAR *, AR1;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura as interrupcoes do nucleo;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #0hSPLK #111111b,IFRSPLK #000001b,IMR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos de I/O;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2SPLK #0000000000000000b,MCRASPLK #1111111000000000b,MCRBSPLK #0000000000101010b,MCRC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos do IOPA como saida;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PADATDIROR #1111111100000000bSACL PADATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos do IOPB como saida;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PBDATDIROR #1111111100000000bSACL PBDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura os pinos do IOPC como saida;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PCDATDIROR #1111111100000000bSACL PCDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura pino IOPE7 como saída;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PEDATDIROR #1000000010000000bSACL PEDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura pinos IOPF 0-6 como entrada;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2LACC PFDATDIRAND #1000000011111111bSACL PFDATDIR;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura o ADC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_PF2SPLK #0100000000000000b, ADCTRL1SPLK #0000000000000011b,MAX_CONVSPLK #0011001000010000b,CHSELSEQ1SPLK #0010000000010000b, ADCTRL1SPLK #1100011000000010b, ADCTRL2;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Config. Full Compare 4,5 e 6 e GP Timer 3;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
266LDP #DP_EVBSPLK #0000h, T3CONSPLK #0000h, T3CNTSPLK #pwm_half_per, T3PRSPLK #0000h, DBTCONBSPLK #0, CMPR4SPLK #0, CMPR5SPLK #0, CMPR6SPLK #0000000010000000b, GPTCONBSPLK #0000000100010001b, ACTRBSPLK #1010001000000000b, COMCONBSPLK #1000100001000100b, T3CON;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Configura as interrupcoes dos EVMs;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~LDP #DP_EVASPLK #0FFFFh, EVAIFRASPLK #0FFFFh, EVAIFRBSPLK #0FFFFh, EVAIFRCSPLK #00000h, EVAIMRASPLK #00000h, EVAIMRBSPLK #00000h, EVAIMRCLDP #DP_EVBSPLK #0FFFFh, EVBIFRASPLK #0FFFFh, EVBIFRBSPLK #0FFFFh, EVBIFRCSPLK #00000h, EVBIMRASPLK #00000h, EVBIMRBSPLK #00000h, EVBIMRC; atualiza os PWMs DA, DB e DC =0LDP #DALACC DALDP #DP_EVBSACL CMPR4LDP #DBLACC DBLDP #DP_EVBSACL CMPR5LDP #DCLACC DCLDP #DP_EVBSACL CMPR6;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Habilita interrupcoes globais;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~CLRC INTM;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Laco principal;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Loop: NOPB loop;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;Rotina de tratamneto da interrupcao ADC;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~adc_isr:;salva contextoMAR *,AR1MAR *+SST #1, *+SST #0, *+SACH *+SACL *+SAR AR2, *+SAR AR0, *+SAR AR3, *+SAR AR4, *+;limpa o INT_FLAG_SEQ1 e le o ADCCLR CSXMLDP #DP_PF2LACC ADCTRL2SACL ADCTRL2;armazena variáveis lidas no ADLACC #0LDP #DP_PF2LACC RESULT3,15LDP #VOSACH VOLACC #0LDP #DP_PF2LACC RESULT2,15LDP #ICSACH ICLACC #0LDP #DP_PF2LACC RESULT1,15LDP #IBSACH IBLACC #0LDP #DP_PF2LACC RESULT0,15LDP #IASACH IA;reset ADC SEQ1 para o estado CONV00LDP #DP_PF2LACC ADCTRL2OR #4000hSACL ADCTRL2;media da tensao de saidaSETC SXMSETC OVMSPM 1LACC #0MPY #0LDP #VOLT VOLDP #KmedMPY KmedAPACLDP #soma_VOADD soma_VO,16SACH soma_VO; partida suave de tensaoLDP #VorefLACC VorefADD #1SACL VorefMAR *,AR4LAR AR4,VorefLDP #VorefnomLAR AR0,VorefnomCMPR 2BCND nlimita, NTCLACC VorefnomLDP #VorefSACL Vorefnlimita:;proteção de tensão minima na malha VMAR *,AR4LDP #VOLAR AR4,VOLDP #VminLAR AR0,VminCMPR 1BCND nreiniciamv, NTCLACC #0LDP #VOLACC VOLDP #VorefSACL VorefLDP #IDLACC IDLDP #IDrefIANTSACL IDrefIANTLDP #IDrefFANTSACL IDrefFANTLDP #IDrefSATANTSACL IDrefSATANTnreiniciamv:;teste de sincronismo - passagem por zero
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FLÁBIO ALBERTO BARDEMAKER BATISTAM
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MODULAÇÃO VETORIAL APLICADA A RET
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Abstract of Thesis presented to UFS
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3.3.1 - Vetores Disponíveis.......
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6.2.2 - Dimensionamento dos Indutor
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B.2 - Netlist para a Simulação do
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LISTA DE SIMBOLOS1. Símbolos Adota
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5. Sub-Índices UtilizadosSímboloS
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2Nesta área, podem ser citados est
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4As referências que tratam deste c
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6PD A1D B1D C1iO ( t)S A1D A3S B1D
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8o Análise da forma de implementa
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10Capítulo 2 - Modulação Vetoria
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12Aplicando a transformação αβ0
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14T 1 representa o intervalo de apl
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16TT′ = ⋅T11 ST1+T2TT′ = ⋅T
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18Tabela 2.6 - Seqüência de vetor
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20A Fig. 2-5 mostra a razão cícli
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22A definição dos setores é infl
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24O sistema original com referencia
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26RSEé a resistência equivalente
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28diA(t) diC(t)2⋅ vA( t) + vC( t)
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30Aplicando esta transformação à
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32Através da Fig. 2-11 é possíve
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34ComoTXD⋅ XD= 1⎡ cos( ω ⋅t)
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536PS A1S B1S C1iO( t )D A1D B1D C1
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38De forma semelhante, foi aplicado
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40200100vAiA( t)( t)0-100-2000s 5ms
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42800mVDbeta( t)Dalfa( t)400mV0V-40
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44As razões cíclicas das fases A,
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46Capítulo 3 - Modulação Vetoria
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48As etapas de operação para o Se
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50Na implementação dos vetores di
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52Tabela 3.2 - Sinais de comando pa
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Page 71 and 72:
56T 02T 12T 2T 12T 02cmd Atcmd Btcm
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58As razões cíclicas dos eixos α
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60Verifica-se também que a distrib
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623.4.1. Cálculos Preliminares e C
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64• Corrente média nos diodos D
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66Tabela 3.11 - Relações entre os
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68s + ωCI( s)=−KI⋅s ⋅ s +ZI(
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70A resposta ao degrau de referênc
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72⎛s + ω V ⎞⎜ ⋅ ⋅lim⎜s
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74A resposta ao degrau de referênc
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76No detalhe da Fig. 3-25 observa-s
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78450V450440V440430420VVo420410400V
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801.0V0.5VDd( t)Dq( t)0V0s 10ms 20m
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8220V20V10VSEL>>0VV(cmd1a)20V10VSEL
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84Os valores apresentados na Tabela
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86Neste caso, são definidos os mes
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884.3. Modulação Vetorial4.3.1. V
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94T 22T 12T 0T 12T 22cmd Atcmd Btcm
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96Neste caso, também se observa qu
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984.4. Dimensionamento do Estágio
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5102As relações para outros sub-s
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104100.0V87.5V75.0V62.5V50.0V30ms 4
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106450V450440V440430420VVo420410400
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1081.0V0.5VDd( t)Dq( t)0V0s 10ms 20
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1101.0uV1.0uV0VSEL>>-1.0uVV(cmd1a)2
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112200V200V0V0V-200V-277V20ms 24ms
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114A Fig. 4-33 mostra a forma de te
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1164.7. ConclusãoO retificador tri
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118Neste caso, são consideradas me
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120120V110V100V90V9.6ms 10.0ms 10.4
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122A Fig. 5-10 apresenta as razões
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124100V75V50V30ms 40ms 60ms 80ms 10
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126450V450440V440430420VVo420410400
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1285.4.1. Vetores Utilizados e Sina
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1305.4.2. Seqüência de Vetores e
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1325.4.3. Modelagem do RetificadorP
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134O projeto dos controladores para
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136Verifica-se a mesma dinâmica ap
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138200vA( t)100iA( t)0-100-2000s 10
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AADa10.90.80.70.60.50.40.30.20.1ALB
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142Como principal diferença entre
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144PPPD A1D B1D C1iO() tD A1D B1D C
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146Neste caso, a razão cíclica n
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148Para uma análise mais aprofunda
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150Tabela 6.1 - Especificações de
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152C2P ⋅ ⋅T= = 4296 μFO hold-u
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156• Perdas totais diodo D 34 :PD
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158RθT− THD34 AHAmax= =PSEMI0,13
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160Para f A= 10 kHz e considerando
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162+15VR493.3k25K13 1C29 2.2pR51R50
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164Saída 2: -15V/500mA para a alim
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1667.2.1. Malha de CorrenteA funç
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168νZIνCI= 2⋅π⋅ fv = 6498 ra
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170• Expressão (7.25): erro de c
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172A freqüência de corte para a m
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174Na Fig. 7-7 é mostrada a respos
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176A posição dos pólos em malha
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178A Fig. 7-14 mostra a lógica uti
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180referênciaNa Fig. 7-19 é mostr
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182O comportamento das razões cíc
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184604020IA,IB,IC (A)0-20-40-600.4
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1867.5. Programação7.5.1. Fluxogr
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188É reservada uma região da mem
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190senoides utilizadas nas transfor
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192vO() ttFig. 7-31 - Comportamento
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1947.5.8. Definição dos Setores e
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196vA () tiA() ta) Tensão de refer
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198A Fig. 8-4 mostra os sinais de c
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200Fig. 8-6 - Razões cíclicas par
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202a) Correntes de entrada para 177
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204Na Fig. 8-10 (a) observa-se a te
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206DA( t )DB( t)DC( t)iA( t )Fig. 8
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208Tabela 8-3 - Comparação entre
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210Neste caso, observa-se uma maior
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212Na Fig. 8-22 (a) observa-se tens
Page 229 and 230: 214Neste caso, observa-se que as fo
Page 231 and 232: 216Estas grandezas apresentam forma
Page 233 and 234: 218VS( t)iS( t )V ( t)D1iD1( t )a)
Page 235 and 236: 2208.5.2. Operação com V L = 380
Page 237 and 238: 222Tabela 8-7 - Fator de potência.
Page 239 and 240: 224Na Fig. 8-41, na Fig. 8-42 e na
Page 241 and 242: 226CONCLUSÃO GERALForam demonstrad
Page 243 and 244: 228dos valores teóricos, validando
Page 245 and 246: 230R83C386.94kV15n714nVo5/400R82 TL
Page 247 and 248: 232V_V46 V15n 0 DC -15D_D43 $N_0005
Page 249 and 250: I234ANEXO B. Diagrama Esquemático
Page 251 and 252: 236um5um1Eq1um1Eq4Dalfa1.225Dalfa1.
Page 253 and 254: 238.ends qualyuniy20k_S36.subckt qu
Page 255 and 256: 240R97C497.7kV15n646nVo5/400R92 TL0
Page 257 and 258: 242E_SUM26 $N_0009 0 VALUE{V($N_001
Page 259 and 260: 244ANEXO D. Dimensionamento do Est
Page 261 and 262: 246D.2. Dimensionamento dos Indutor
Page 263 and 264: 248⎧ vA(t) + vB(t) + vC(t) = 0⎪
Page 265 and 266: 250P 0,613⋅V −2⋅η⋅VI = ⋅
Page 267 and 268: 252ππ⎧⎫6 61 ⎪⎪IS = ⋅⎨
Page 269 and 270: 254ID3456MEDdiodos D I3456 .0⎧⎫
Page 271 and 272: 256ANEXO E. Esquemas Elétricos das
Page 273 and 274: 258C7100pF1110U2ALF347324111+-V+V-O
Page 275 and 276: 260GNDVsincA10k56nR54C31+15VR473.3k
Page 277 and 278: 262Barra de PinosBarra de Pinos1Bar
Page 279: 264int10: B int10int11: B int11int1
Page 283 and 284: 268SACL IDrefSATMAR *,AR4LDP #IDref
Page 285 and 286: 270; Dqlinha (total)LDP #DqlinhaPAD
Page 287 and 288: 272LDP #KD_1LT KD_1MPY DalfaSPACLDP
Page 289 and 290: 274CLRC SXMCLRC OVM; testa Inibe pa
Page 291 and 292: 276REFERÊNCIAS BIBLIOGRÁFICAS[1]
Page 293 and 294: 278[21] AREDES, M.; Active Power Li
Page 295 and 296: 280[44] BOTTERÓN, F.; Análise, Pr
Page 297: 282[67] BORGONOVO, Deivis; Análise
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ModulaÃ§Ã£o Vetorial Aplicada ao Retificador TrifÃ¡sico PWM - Ivo Barbi

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