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A B S T R A C T
The inner-product operation is frequently used in many Digital Signal
Processing, for example filtering, matrix multiplication and vector
multiplication, correlation and others. The velocity performance of these
algorithms depends strongly on the performance of this operation. Therefore,
many architectures have been proposed in the literature to enhance the
performance of the inner-product operation. One of these architectures, which
has been extensively used in high speed applications, is the systolic
structures. These structures are very appealing to VLSI implementation of
real-time and massive processing systems, specially because of its
characteristics of modularity, regularity, local connections and high level
of parallelism and pipelining.
This work will propose new systolic structures based on cells processing
words of n/k-bits width to realize the inner-product operation efficiently,
namely, with high performance and low design costs. The results of the
simulatíons, comparisons and implementations will assure that the proposed
structures are an excellent alternative to realize many algorithms based on
the inner-product operation. Moreover, these structures have performances of
velocity and required area dependable on k value, namely, partition level of
the input words. This characteristic gives a flexibility to system designer
allowing to choice one of the structures proposed which satisfy the trade off
between area and performance of the involved application.