power monitors are on an independent i2c bus - Spectrum Digital ...

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54321This section is an outline of vias labeled as Testpoints in the schematic. This allows us to determine pwb line lengths for memory tomemory and CPU to memory it is purely a visibility tool no actual "component" is used the vias <strong>are</strong> just replaced with a via that islabeled a test pointMEMORY 4MEMORY 1 MEMORY 2MEMORY 3DD18,37,39 DDR0_A0DDR0_A01TPM181TPMB181TPMC181TPMD1818,37,39 DDR0_A1DDR0_A11TPM191TPMB191TPMC191TPMD1918,37,39 DDR0_A2DDR0_A21TPM171TPMB171TPMC171TPMD1718,37,39 DDR0_A3DDR0_A31TPM111TPMB111TPMC111TPMD1118,37,39 DDR0_A4DDR0_A41TPM201TPMB201TPMC201TPMD2018,37,39 DDR0_A5DDR0_A51TPM161TPMB161TPMC161TPMD1618,37,39 DDR0_A6DDR0_A61TPM241TPMB241TPMC241TPMD2418,37,39 DDR0_A7DDR0_A71TPM211TPMB211TPMC211TPMD2118,37,39 DDR0_A8DDR0_A81TPM271TPMB271TPMC271TPMD27C18,37,39 DDR0_A918,37,39 DDR0_A10DDR0_A9DDR0_A1011TPM22TPM911TPMB22TPMB911TPMC22TPMC911TPMD22TPMD9C18,37,39 DDR0_A11DDR0_A111TPM231TPMB231TPMC231TPMD2318,37,39 DDR0_A12DDR0_A121TPM141TPMB141TPMC141TPMD1418,37,39 DDR0_A13DDR0_A131TPM251TPMB251TPMC251TPMD2518,37,39 DDR0_A14DDR0_A141TPM261TPMB261TPMC261TPMD2618,37,39 DDR0_A15DDR0_A151TPM101TPMB101TPMC101TPMD1018,37,39 DDR0_BA0DDR0_BA01 TPM121 TPMB121TPMC121TPMD1218,37,39 DDR0_BA1DDR0_BA11TPM151TPMB151TPMC151TPMD1518,37,39 DDR0_BA2DDR0_BA21TPM131TPMB131TPMC131TPMD1318,37,39 DDR0_RASNDDR0_RASN1TPM11TPMB11TPMC11TPMD118,37,39 DDR0_CASNDDR0_CASN1TPM21TPMB21TPMC21TPMD2B18,37,39 DDR0_WEN18,37,39 DDR0_ODT0DDR0_WENDDR0_ODT011TPM8TPM611TPMB8TPMB611TPMC8TPMC611TPMD8TPMD6B18,37,39 DDR0_CKEDDR0_CKE1TPM51TPMB51TPMC51TPMD518,37,39 DDR0_CSN0DDR0_CSN01TPM71TPMB71TPMC71TPMD718,37,39 DDR0_CLK0DDR0_CLK01TPM31TPMB31TPMC31TPMD318,37,39 DDR0_CLK0NDDR0_CLK0N1TPM41 TPMB41 TPMC41TPMD4ATEXAS INSTRUMENTS INCORPORATEDATitle:Page Contents:J5 ECO EVMTEST POINTS EMIF0Size: BDWG NO515062-0001Revision:ADate: Monday, January 16, 2012 Sheet 36 o f 6454321
5544332211DDCCBBAADDR0_RSTDDR0_RSTZQ_DBYTE1 ZQ_DBYTE2 ZQ_DBYTE3 ZQ_DBYTE4DDR0_RST DDR0_RST DDR0_RSTDDR0_A7DDR0_A5DDR0_A8DDR0_BA1DDR0_CASnDDR0_BA2DDR0_A0DDR0_A4DDR0_A6DDR0_CSN0DDR0_A3DDR0_A11DDR0_A14DDR0_A1DDR0_CKEDDR0_A12DDR0_CLK0DDR0_CLK0NDDR0_RASnDDR0_ODT0DDR0_WEnDDR0_BA0DDR0_A13DDR0_A2DDR0_A9DDR0_A10DDR_VREFSSTLVDD_DDRDDR_VREFSSTLDDR0_A15DDR0_DQM0DDR0_DQSN0DDR0_DQS0DDR0_DQM1DDR0_DQSN1DDR0_DQS1DDR0_DQM2DDR0_DQSN2DDR0_DQS2DDR0_DQM3DDR0_DQSN3DDR0_DQS3DDR_VREFSSTL DDR_VREFSSTL DDR_VREFSSTLDDR0_D3DDR0_D7DDR0_D4DDR0_D5DDR0_D6DDR0_D0DDR0_D1DDR0_D2DDR0_D11DDR0_D15DDR0_D12DDR0_D13DDR0_D14DDR0_D8DDR0_D9DDR0_D10DDR0_D19DDR0_D23DDR0_D20DDR0_D21DDR0_D22DDR0_D16DDR0_D17DDR0_D18DDR0_D27DDR0_D31DDR0_D28DDR0_D29DDR0_D30DDR0_D24DDR0_D25DDR0_D26DDR0_DQM0DDR0_DQM1DDR0_DQM2DDR0_DQM3DDR0_DQS0DDR0_DQS1DDR0_DQS2DDR0_DQS3DDR0_DQSN0DDR0_DQSN1DDR0_DQSN2DDR0_DQSN3DDR0_A7DDR0_A5DDR0_A8DDR0_A0DDR0_A4DDR0_A6DDR0_A3DDR0_A11DDR0_A14DDR0_A1DDR0_A12DDR0_A13DDR0_A2DDR0_A9DDR0_A10DDR0_A15DDR0_A7DDR0_A5DDR0_A8DDR0_A0DDR0_A4DDR0_A6DDR0_A3DDR0_A11DDR0_A14DDR0_A1DDR0_A12DDR0_A13DDR0_A2DDR0_A9DDR0_A10DDR0_A15DDR0_A7DDR0_A5DDR0_A8DDR0_A0DDR0_A4DDR0_A6DDR0_A3DDR0_A11DDR0_A14DDR0_A1DDR0_A12DDR0_A13DDR0_A2DDR0_A9DDR0_A10DDR0_A15DDR0_A7DDR0_A5DDR0_A8DDR0_A0DDR0_A4DDR0_A6DDR0_A3DDR0_A11DDR0_A14DDR0_A1DDR0_A12DDR0_A13DDR0_A2DDR0_A9DDR0_A10DDR0_A15DDR0_BA1DDR0_BA2DDR0_BA0DDR0_BA1DDR0_BA2DDR0_BA0DDR0_BA1DDR0_BA2DDR0_BA0DDR0_BA1DDR0_BA2DDR0_BA0DDR0_CASnDDR0_CSN0DDR0_CKEDDR0_RASnDDR0_ODT0DDR0_WEnDDR0_CASnDDR0_CSN0DDR0_CKEDDR0_RASnDDR0_ODT0DDR0_WEnDDR0_CASnDDR0_CSN0DDR0_CKEDDR0_RASnDDR0_ODT0DDR0_WEnDDR0_CASnDDR0_CSN0DDR0_CKEDDR0_RASnDDR0_ODT0DDR0_WEnDDR0_CLK0NDDR0_CLK0DDR0_CLK0NDDR0_CLK0DDR0_CLK0NDDR0_CLK0DDR0_CLK0NDDR0_CLK0DDR0_D3DDR0_D7DDR0_D4DDR0_D5DDR0_D6DDR0_D0DDR0_D1DDR0_D2DDR0_D11DDR0_D15DDR0_D12DDR0_D13DDR0_D14DDR0_D8DDR0_D9DDR0_D10DDR0_D19DDR0_D23DDR0_D20DDR0_D21DDR0_D22DDR0_D16DDR0_D17DDR0_D18DDR0_D27DDR0_D31DDR0_D28DDR0_D29DDR0_D30DDR0_D24DDR0_D25DDR0_D26VDD_DDR VDD_DDR VDD_DDR VDD_DDRDDR_VREFSSTLVDD_DDRDDR_VREFSSTLVDD_DDRDDR_VREFSSTLVDD_DDRDDR_VREFSSTLVDD_DDRDDR_VREFSSTLVDD_DDRDDR0_RST18DDR0_CLK018,36,39DDR0_CLK0N18,36,39DDR0_CKE18,36,39DDR0_A018,36,39DDR0_A118,36,39DDR0_A218,36,39DDR0_A318,36,39DDR0_A418,36,39DDR0_A518,36,39DDR0_A618,36,39DDR0_A718,36,39DDR0_A818,36,39DDR0_A918,36,39DDR0_A1018,36,39DDR0_A1118,36,39DDR0_A1418,36,39DDR0_BA018,36,39DDR0_BA118,36,39DDR0_BA218,36,39DDR0_CSN018,36,39DDR0_RASN18,36,39DDR0_CASN18,36,39DDR0_WEN18,36,39DDR0_ODT018,36,39DDR0_A1318,36,39DDR0_A1218,36,39DDR_VREFSSTL 18,57VDD_DDR 38,39,55,57DDR0_A1518,36,39DDR0_D018DDR0_D118DDR0_D218DDR0_D318DDR0_D418DDR0_D518DDR0_D618DDR0_D718DDR0_D818DDR0_D918DDR0_D1018DDR0_D1118DDR0_D1218DDR0_D1418DDR0_D1518DDR0_D1618DDR0_D1718DDR0_D1818DDR0_D1918DDR0_D2018DDR0_D2118DDR0_D2218DDR0_D2318DDR0_D2418DDR0_D2518DDR0_D2618DDR0_D2718DDR0_D2818DDR0_D2918DDR0_D3018DDR0_D3118DDR0_D1318DDR0_DQM018DDR0_DQM118DDR0_DQM218DDR0_DQM318DDR0_DQS018DDR0_DQS118DDR0_DQS218DDR0_DQS318DDR0_DQSN018DDR0_DQSN118DDR0_DQSN218DDR0_DQSN318Size:Date:DWG NORevision:Sheeto fTitle:Page Contents:ATEXAS INSTRUMENTS INCORPORATED515062-0001Monday, January 16, 2012 37 64BJ5 ECO EVMDDR3 MEMORYR541240C4310.22uFC4370.22uFU58MT41J128M8JP-125:GDQ0B3DQ1C7DQ2C2DQ3C8DQ4E3DQ5E8DQ6D2DQ7E7A0K3A1L7A2L3A3K2A4L8A5L2A6M8A7M2A8N8A9M3A10/APH7A11M7A12/BCK7A13N3BA0J2BA1K8BA2J3CKEG9CSH2ODTG1RASF3CASG3WEH3RESETN2DQSC3DQSD3DM/TDQSB7TDQSA7VDD.1A2VDD.2A9VDD.3D7VDD.4G2VDD.5G8VDD.6K1VDD.7K9VDD.8M1VDD.9M9VDDQ.1B9VDDQ.2C1VDDQ.3E2VDDQ.4E9VREFCAJ8VREFDQE1VSS.1A1VSS.2A8VSS.3B1VSS.4D8VSS.5F2VSS.6F8VSS.7J1VSS.8J9VSS.9L1VSS.10L9VSS.11N1VSS.12N9VSSQD9VSSQD1VSSQC9VSSQB8VSSQB2ZQH8NC.1A3NC.2F1NC.3F9NC.4H1NC.5H9A15/NCJ7CKF7CKG7A14/NCN7U59MT41J128M8JP-125:GDQ0B3DQ1C7DQ2C2DQ3C8DQ4E3DQ5E8DQ6D2DQ7E7A0K3A1L7A2L3A3K2A4L8A5L2A6M8A7M2A8N8A9M3A10/APH7A11M7A12/BCK7A13N3BA0J2BA1K8BA2J3CKEG9CSH2ODTG1RASF3CASG3WEH3RESETN2DQSC3DQSD3DM/TDQSB7TDQSA7VDD.1A2VDD.2A9VDD.3D7VDD.4G2VDD.5G8VDD.6K1VDD.7K9VDD.8M1VDD.9M9VDDQ.1B9VDDQ.2C1VDDQ.3E2VDDQ.4E9VREFCAJ8VREFDQE1VSS.1A1VSS.2A8VSS.3B1VSS.4D8VSS.5F2VSS.6F8VSS.7J1VSS.8J9VSS.9L1VSS.10L9VSS.11N1VSS.12N9VSSQD9VSSQD1VSSQC9VSSQB8VSSQB2ZQH8NC.1A3NC.2F1NC.3F9NC.4H1NC.5H9A15/NCJ7CKF7CKG7A14/NCN7U60MT41J128M8JP-125:GDQ0B3DQ1C7DQ2C2DQ3C8DQ4E3DQ5E8DQ6D2DQ7E7A0K3A1L7A2L3A3K2A4L8A5L2A6M8A7M2A8N8A9M3A10/APH7A11M7A12/BCK7A13N3BA0J2BA1K8BA2J3CKEG9CSH2ODTG1RASF3CASG3WEH3RESETN2DQSC3DQSD3DM/TDQSB7TDQSA7VDD.1A2VDD.2A9VDD.3D7VDD.4G2VDD.5G8VDD.6K1VDD.7K9VDD.8M1VDD.9M9VDDQ.1B9VDDQ.2C1VDDQ.3E2VDDQ.4E9VREFCAJ8VREFDQE1VSS.1A1VSS.2A8VSS.3B1VSS.4D8VSS.5F2VSS.6F8VSS.7J1VSS.8J9VSS.9L1VSS.10L9VSS.11N1VSS.12N9VSSQD9VSSQD1VSSQC9VSSQB8VSSQB2ZQH8NC.1A3NC.2F1NC.3F9NC.4H1NC.5H9A15/NCJ7CKF7CKG7A14/NCN7R540240C4380.22uFC4390.22uFC4410.22uFC4330.22uFC4320.22uFC4340.22uFR538240R539240U57MT41J128M8JP-125:GDQ0B3DQ1C7DQ2C2DQ3C8DQ4E3DQ5E8DQ6D2DQ7E7A0K3A1L7A2L3A3K2A4L8A5L2A6M8A7M2A8N8A9M3A10/APH7A11M7A12/BCK7A13N3BA0J2BA1K8BA2J3CKEG9CSH2ODTG1RASF3CASG3WEH3RESETN2DQSC3DQSD3DM/TDQSB7TDQSA7VDD.1A2VDD.2A9VDD.3D7VDD.4G2VDD.5G8VDD.6K1VDD.7K9VDD.8M1VDD.9M9VDDQ.1B9VDDQ.2C1VDDQ.3E2VDDQ.4E9VREFCAJ8VREFDQE1VSS.1A1VSS.2A8VSS.3B1VSS.4D8VSS.5F2VSS.6F8VSS.7J1VSS.8J9VSS.9L1VSS.10L9VSS.11N1VSS.12N9VSSQD9VSSQD1VSSQC9VSSQB8VSSQB2ZQH8NC.1A3NC.2F1NC.3F9NC.4H1NC.5H9A15/NCJ7CKF7CKG7A14/NCN7
Page 2: 54321DDEVM_1V8_CPU E7NFM21PC474R1C3
Page 5 and 6: 543214 DCAN1_RX4 DCAN1_TXJP3DCAN1_R
Page 7 and 8: 54321EVM_3V3DDR29710K16 GPMC_WAITGP
Page 9 and 10: 54321DDU42-16SD0_CLK/EHRPWM2A/GP0[1
Page 11 and 12: 54PLACE 100 OHM RESISTORS AT CPU321
Page 13 and 14: 54321D40 GPMC_EMAC_SW_SEL31 GP5[4]1
Page 15 and 16: 54321VUSB_3V33.3 VOLTDC2610.1uFC272
Page 17 and 18: 5544332211DDCCBBAAGPMC_WPNOPT_SW1EV
Page 19 and 20: 54321U42-9VOUT[0]_CLKVOUT[0]_HSYNC/
Page 21 and 22: 54321EVM_3V3U87SEL_HDMI_EXP_S0SEL_H
Page 23 and 24: 54321EVM_5V0DC19 LCD_DE19 LCD_HS19
Page 25 and 26: 54321U16SiI9022ACNU9122_CVCC9122_CV
Page 27 and 28: 543213V3_VDDA3V3_VDDA3V3_VDDADR371
Page 29 and 30: 54321EVM_5V0EVM_3V3EVM_3V3EVM_3V3 E
Page 31 and 32: 54321EVM_3V3BCK2_3V3R35410KC2430.1u
Page 33 and 34: 5544332211DDCCBBAACORE_VDDCORE_VDDD
Page 35: 5544332211DDCCBBAASize:Date:DWG NOR
Page 39 and 40: 54321VDD_DDRVDD_DDRVDD_DDR 37,38,55
Page 41 and 42: 54321EVM_5V0L16NO-POPL15BLM18AG221S
Page 43 and 44: 54321EVM_3V6EVM_1V8P8DCB42 SLEEP_CL
Page 45 and 46: 54321EVM_3V3L10AVDD3V3_ENET0ADVDDL_
Page 47 and 48: 54321DEVM_3V3EVM_3V3R4942KSW7ON1 1
Page 49 and 50: 54321DDJ15CEVM_3V35C297.1uFEVM_3V3R
Page 51 and 52: 54321DDJ14CSPI1_CLK4,6 SPI[1]_SCLK1
Page 53 and 54: 54321C17410uFEVM_5V0VBACKUPC59 0.1u
Page 55 and 56: 54321VDD_CDCE2NFM21PC474R1C3D1 3VUS
Page 57 and 58: 54321DEVM_5V0EVM_5V0DEVM_5V0R4NO-PO
Page 59 and 60: 54321EVM_5V0EVM_12VEVM_5V0EVM_5V0DR
Page 61 and 62: 54321DDEVM_5V0U63TPS74701EVM_3V6CC1
Page 63 and 64: 54321DD12 VOLTS5 VOLTS3V3 VOLTSCCBB

power monitors are on an independent i2c bus - Spectrum Digital ...

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