SEP 40
SEP 40 SEP 40
grifo ® ITALIAN TECHNOLOGY THE RECOMMENDED ISP CONNECTOR LAYOUT IN TARGET SYSTEM This interface corresponds with Atmel application note AVR910: In-System Programming. This application note is used in every ISP programmer and describes the recommended ISP interface connector layout in target system (top view in figure 6). PIN NAME PURPOSE SCK Serial Clock MOSI MISO RESET Vcc GND Master Out Slave In Master In Slave Out Target MCU Reset Target Power Supply Common Ground Programming clock, generated by the In-System programmer (master). Communication line from In-System programmer (master) to target MCU being programmed (slave). Communication line from target MCU (slave) to In- System programmer (master). To enable In-System programming, the target MCU Reset must be kept active. To simplify this, the In-System programmer should control the target MCU Reset The target can have power supplied through the In-System programming connector for the duration of the programming cycle. Target system cannot supply SEP 40. The two systems must share the same common ground. FIGURE 4: ISP PINOUT Specification of ISP connector pins depends on programming device and is displayed at Additional info window. This specification corespond with application notes publised of device manufacturers. Note: Pin no. 1 is signed by triangle scratch on ISP cable connectors. H/L/read SEP 40 driver is shown on figure 7. Warnings: - When you use SEP 40 as ISP programmer, don’t insert device to ZIF socket. - When you programm devices in ZIF sosket, don’t insert ISP cable to ISP connector. - Use only attached ISP cable. When you use other ISP cable (other material, length…), programming may occour unreliable. - SEP 40 can supply target device (target system with limitation), but target system cannot supply SEP 40. - SEP 40 apply programming voltage to target device and checks his value (target system can modify programming voltage). If the programming voltage is different as expected, no action with target device will be executed. Page 66 SEP 40 Rel. 3.10
ITALIAN TECHNOLOGY grifo ® SEP 40 Rel. 3.10 FIGURE 5: ISP CONNECTION EXAMPLE Vcc MISO 1 2 SCK 3 4 MOSI RESET 5 6 GND FIGURE 6: TARGET BOARD SUGGESTED ISP CONNECTOR H/L/read driver Correspondance between ISP signals and connector pins may vary according to the device to be programmed. To know this correspondance, please select the device desired in the control program (menu Device / Select Device) and press “Additional Info” button or press Ctrl+F1. 1n0 1k3 FIGURE 7: ISP DRIVER OF SEP 40 FIGURE 8: ISP CONNECTOR OF SEP 40 ISP connector 9 10 7 8 5 6 3 4 1 2 Page 67
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grifo ® ITALIAN TECHNOLOGY<br />
THE RECOMMENDED ISP CONNECTOR LAYOUT IN TARGET SYSTEM<br />
This interface corresponds with Atmel application note AVR910: In-System Programming. This<br />
application note is used in every ISP programmer and describes the recommended ISP interface<br />
connector layout in target system (top view in figure 6).<br />
PIN NAME PURPOSE<br />
SCK Serial Clock<br />
MOSI<br />
MISO<br />
RESET<br />
Vcc<br />
GND<br />
Master Out<br />
Slave In<br />
Master In<br />
Slave Out<br />
Target MCU<br />
Reset<br />
Target Power<br />
Supply<br />
Common<br />
Ground<br />
Programming clock, generated by the In-System<br />
programmer (master).<br />
Communication line from In-System programmer<br />
(master) to target MCU being programmed (slave).<br />
Communication line from target MCU (slave) to In-<br />
System programmer (master).<br />
To enable In-System programming, the target MCU Reset<br />
must be kept active. To simplify this, the In-System<br />
programmer should control the target MCU Reset<br />
The target can have power supplied through the In-System<br />
programming connector for the duration of the<br />
programming cycle. Target system cannot supply <strong>SEP</strong> <strong>40</strong>.<br />
The two systems must share the same common ground.<br />
FIGURE 4: ISP PINOUT<br />
Specification of ISP connector pins depends on programming device and is displayed at Additional<br />
info window. This specification corespond with application notes publised of device manufacturers.<br />
Note: Pin no. 1 is signed by triangle scratch on ISP cable connectors.<br />
H/L/read <strong>SEP</strong> <strong>40</strong> driver is shown on figure 7.<br />
Warnings:<br />
- When you use <strong>SEP</strong> <strong>40</strong> as ISP programmer, don’t insert device to ZIF socket.<br />
- When you programm devices in ZIF sosket, don’t insert ISP cable to ISP connector.<br />
- Use only attached ISP cable. When you use other ISP cable (other material, length…),<br />
programming may occour unreliable.<br />
- <strong>SEP</strong> <strong>40</strong> can supply target device (target system with limitation), but target system cannot supply<br />
<strong>SEP</strong> <strong>40</strong>.<br />
- <strong>SEP</strong> <strong>40</strong> apply programming voltage to target device and checks his value (target system can<br />
modify programming voltage). If the programming voltage is different as expected, no action<br />
with target device will be executed.<br />
Page 66 <strong>SEP</strong> <strong>40</strong> Rel. 3.10
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