LEZIONE #05 del 12-Mag-2008 (2 ore) - Dipartimento di Ingegneria ...

Prestazioni
• Confronto tra due generazioni di architetture Intel (130nm vs 90nm)
SPECint_base2000 130nm 90nm
164.gzip 1.03 1.01
175.vpr 1.32 1.21
176.gcc 0.85 0.70
181.mcf 1.35 1.22
186.crafty 0.72 0.69
197.parser 1.06 0.87
252.eon 0.44 0.39
253.perlbmk 0.62 0.28
254.gap 0.33 0.24
255.vortex 0.08 0.09
256.bzip2 1.19 1.12
300.twolf 1.32 1.23
Roberto Giorgi, Universita’ di Siena, C208L05, Slide 39
References
Nella tabella a lato si riporta il numero
di misprediction su 100 istruzioni di
branch, nal caso dell’architettura P4 a
130 nm e a 90 nm.
Dati forniti da Intel.
[Alpha99] Compaq Computer Corporation, Alpha 21264 Microprocessor Hardware Reference
Manual, 1999.
[Boggs03] Boggs D., et. al. The Microarchitecture of the Intel ® Pentium ® 4 Processor on 90nm
Technology. Intel ® Technology Journal, Vol 08, Issue 01, February 18, 2003.
[Gochman03] Gochman S., et. al. The Intel ® Pentium ® M Processor: Microarchitecture and
Performance. Intel ® Technology Journal, Vol 07, Issue 02, May 21, 2003.
[Hennessy02] Hennessy, J. L. and Patterson, D. A. 2002 Computer Architecture: a Quantitative
Approach. 3 rd Edition. Morgan Kaufmann Publishers Inc. 2002.
[Kaeli91] D. R. Kaeli and P. G. Emma. Branch history table prediction of moving target
branches due to subroutine returns. In Proc. ISCA-18, pages 34–41, May 1991.
[McFarling93] McFarling, S . Combining Combining branch branch predictors. predictors. Technical Report TN-36, Digital
Western Research Laboratory, June 1993.
[Pan92] S. T. Pan, K. So, and J. T. Rahmeh. Improving the accuracy of dynamic branch
prediction using branch correlation. In Proceedings of ASPLOS V, pages 76–84,
Boston, MA, October 1992.
[Shen02] Shen J. P. , Lipasti M. Modern Processor Design, McGraw Hill Higher Education;
Beta Ed edition (November 1, 2002).
[Yeh93-ics] Yeh, T., Marr, D. T., and Patt, Y. N. 1993. Increasing the instruction fetch rate via
multiple branch prediction and a branch address cache. In Proceedings of the 7th
International Conference on Supercomputing (Tokyo, Japan, July 19 - 23, 1993).
[Uht95] Uht, A. K., Sindagi, V., Hall, K. Disjoint eager execution: an optimal form of
speculative execution. In Proceedings of the 28th Annual international Symposium
on Microarchitecture (Dec. 1995).
Roberto Giorgi, Universita’ di Siena, C208L05, Slide 40