ETTC'2003 - SEE
ETTC'2003 - SEE ETTC'2003 - SEE
The index multiplier block will be evaluated in an FPGA logic block as well as in the RAM block. Decimation Filters In a two’s complementary based decimation filter, the required word length may vary between 40 and 56 bits. It depends on the decimation factor and the bandwidth n n n−1 n−2 characteristics. In our evaluation, the selected moduli type is 2,2−1,2−1,2− 1 and n will vary between 11 and 15. As the dynamic range changes from application to application, a software RNS calculator is developed. A part of the calculator display is given below.
The decimation processing flow is given below Input Data Binary - RNS Conversion Processing flow Processor m 1 Processor m n Overflow detection by a redundant RNS module RNS -Binary Conversion:CRT/MRC Output Data
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The decimation processing flow is given below<br />
Input Data<br />
Binary - RNS<br />
Conversion<br />
Processing flow<br />
Processor m 1<br />
Processor m n<br />
Overflow detection by a<br />
redundant RNS module<br />
RNS -Binary<br />
Conversion:CRT/MRC<br />
Output Data
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