ETTC'2003 - SEE
ETTC'2003 - SEE ETTC'2003 - SEE
Binary X Binary to RNS and RNS to Binary dataflow Binary to RNS Conversion RNS Processor RNS Processor RNS Processor DSP Algorithm Binary to RNS Conversion CRT/MRC output Y 1.1.4. Conclusion 1. RNS is an integer system 2. Addition, subtraction and multiplication are fast 3. Division is a complex process but certain stipulations are defined which allow for the inverse of a number to exist. 4. RNS is not a weighted number system which means that magnitude comparison, sign detection and overflow detections properties are not embedded. One needs to use MRC for implementation. 1.2. Reconfigurable embedded cores IF FrontEnd The object of the current program is to develop embedded cores based on RNS for system level applications. In order to evaluate the performance, the Digital Down Converter (DDC) has been selected. The digital down converter is made of three cores, a NCO (Numerical Control Oscillator), a mixer and decimation filters. The NCO provides a small frequency resolution with fast frequency switching. The conceptual view of the DDC is given below: ADC L X X Phase Accumulator L Reg AGC and CIC W NCO ROM AGC and CIC AGC and CIC AGC and CIC I FI R Q
The processing flow for the down converter is given below : Read_Data () ; Read data from ADC Convert_RNS_Index () ; Prepare for index multiplication Index_Mixer ( ) ; NCO output and sampled RF data multiplication Decimation_Filter ( ) ; Down sampling Conversion_RNS2Binary ( ) ; RNS to binary conversion NCO block The NCO is made of two parts: a phase accumulator and a waveform table in the ROM. The phase accumulator adder needs to be very fast in order to achieve its highest performance but for wide accumulators the propagation delay will limit the performance. An RNS based NCO was proposed by Chren [7]. In this RNS_NCO the phase accumulator is based on a moduli and the scalar performs the truncation between the phase accumulator output and the ROM. The conceptual view is given below. Moduli RNS ACCU RNS ACCU Phase accumulator Scalar Address Control RNS_NCO ROM RNS Processor In the above implementation, the phase accumulator is based on n channels with a very complex scalar hardware module. The scalar hardware is needed for the truncation of the phase accumulator output before being addressed to the ROM. The study currently focuses on how to reduce the complexity of the scalar circuit as well as look at alternative hardware structures to reduce the complexity for the FPGA implementation. Mixer block In a DDS, the incoming IF (Intermediate Frequency) data samples need to be mixed (multiplier) with the NCO output signals which are performed using an index calculus method. This index multiply technique uses the Galois field theory [8,9,10]; given a Galois field GF(p), where p is a prime number , it is possible to generate all non zero elements by using a primitive root of p. This approach requires following steps Index_Calculation ( ) Addition_Modulo_p-1 ( ) Reverse Index _Calculation ( )
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The processing flow for the down converter is given below :<br />
Read_Data () ; Read data from ADC<br />
Convert_RNS_Index () ; Prepare for index multiplication<br />
Index_Mixer ( ) ; NCO output and sampled RF data multiplication<br />
Decimation_Filter ( ) ; Down sampling<br />
Conversion_RNS2Binary ( ) ; RNS to binary conversion<br />
NCO block<br />
The NCO is made of two parts: a phase accumulator and a waveform table in the<br />
ROM. The phase accumulator adder needs to be very fast in order to achieve its<br />
highest performance but for wide accumulators the propagation delay will limit the<br />
performance. An RNS based NCO was proposed by Chren [7]. In this RNS_NCO the<br />
phase accumulator is based on a moduli and the scalar performs the truncation<br />
between the phase accumulator output and the ROM. The conceptual view is given<br />
below.<br />
Moduli<br />
RNS<br />
ACCU<br />
RNS<br />
ACCU<br />
Phase<br />
accumulator<br />
Scalar<br />
Address<br />
Control<br />
RNS_NCO<br />
ROM<br />
RNS<br />
Processor<br />
In the above implementation, the phase accumulator is based on n channels with a<br />
very complex scalar hardware module. The scalar hardware is needed for the<br />
truncation of the phase accumulator output before being addressed to the ROM. The<br />
study currently focuses on how to reduce the complexity of the scalar circuit as well as<br />
look at alternative hardware structures to reduce the complexity for the FPGA<br />
implementation.<br />
Mixer block<br />
In a DDS, the incoming IF (Intermediate Frequency) data samples need to be mixed<br />
(multiplier) with the NCO output signals which are performed using an index calculus<br />
method. This index multiply technique uses the Galois field theory [8,9,10]; given a<br />
Galois field GF(p), where p is a prime number , it is possible to generate all non zero<br />
elements by using a primitive root of p. This approach requires following steps<br />
Index_Calculation ( )<br />
Addition_Modulo_p-1 ( )<br />
Reverse Index _Calculation ( )