ETTC'2003 - SEE

BACK
FINITE ARITHMETIC CONCEPTS AND EMBEDDED DSP CORES
FOR RECONFIGURABLE COMMUNICATION SYSTEMS
Henry Chandran Pierre-Yves DUSSAUZE
Signal Processing Group
Navtel Systems SA CNES – Toulouse
France France
hchandran@compuserve.com Pierre-Yves.Dussauze@cnes.fr
Abstract
Reconfigurable computing platforms have started to replace traditional hardware in
terms of cost effectiveness and performance over a wide range of applications. These
computing platforms are based on two’s complement arithmetic which lacks precision
and speed to handle Digital RF band signal processing. This led to search for an
alternative binary weighted digital system such as RNS (Residue Number System) to
develop high bandwidth low power embedded DSP cores for system level
applications. The RNS is a carry free system with no performance degradation when
increasing the word width. This allows to select an arbitrary word length in order to
optimise the special signal processing core. This study is carried out by Navtel
Systems in collaboration with the CNES (Centre National d’Etudes Spatiales).
Keywords
Forward Error Corrector
Digital Down Converter
Modulation demodulation
Neural network
OFDM
Reconfigurable hardware
Residue Number System
Synchronisation
Introduction
Today’s communication systems are made of multiple embedded DSP cores. The
processing operations are performed by two groups of instructions : addition,
subtraction and multiplication and division, scaling and magnitude comparison. The
hardware for these instructions are based on two’s complement because of its
simplicity. An arithmetic alternative exists ; this is the modular arithmetic known as
RNS and only used in special computing such as signal processing where it increases
the processing power with reduced power consumption.