ETTC'2003 - SEE
ETTC'2003 - SEE ETTC'2003 - SEE
shown below together with the AGE chassis from which it was developed. Figure 1: IENA-N2-AFDX concentrator (Lab version) Figure 2: AGE chassis (EADS Military Aircraft) Datation Data acquired by a complex aircraft test system can only be analyzed if data originating from different instruments (parameters) can be precisely correlated in time. The IENA system requires global datation (time-stamping) of all acquired parameters with a 0.5 microsecond precision and a 1 microsecond 48-bit wide resolution for long-term applications. The system must be synchronized with an external GPS time source in order to be able to correlate data acquired by independent test systems. During the IENA modeling phase, CES developed a global synchronization system meeting these requirements. This system was first used for time-stamping PCM data acquired by the MFCC 8441 based PCM 5367 function unit. An enhanced version of this system, which allows direct IRIG-B input into the datation master unit (DAT 5384), is part of the IENA-N2 AFDX concentrator. Independently, the AIDASS system uses a system wide time-stamping mechanism with 10 microseconds precision, but without direct GPS synchronization (timestamp counters start counting from zero after system reset). With the integration of the AFDX general test resource into AIDASS both time-stamping methods will be supported b y the system. Since this function is implemented in the application specific FPGA of the MFCC, it is also feasible to directly integrate the IENAstyle datation method into a variant of the MIL 1553 and EFABUS function unit. For the next generation of CES PPC SBCs (RIO4, s. below), the integration of a GPS receiver directly on board (no PMC), as well as an on board solid state disk is foreseen. Next generation By the end of 2003, CES plans to have the first units of its new generation of boards operational. All boards in this family will use Xilinks Virtex II Pro FPGAs in which part of the available logic is reserved for application specific developments. The remaining FPGA resources will be used to implement powerful bus interfaces (e.g. VME 2eSST) and a sophisticated monitor and control system which allows to subdivede a system composed of SBCs and PMCs into secure cells, functional subunits which can be individually reconfigured and re-started without the need for a global system reset. The new family consists of • The RIO4 8070, a VME SBC with up to two PPC 7457 CPUs, up to 2 GBytes of main memory, 10-
1000Mbit Ethernet, GPS receiver on board and a set of high-speed serial links for application specific needs. • The MFCC 8447, a successor of the MFCC 8441 and MFCC 8443 is a PMC with PPC 750FX, up to 256 Mbytes of main memory and most of the Virtex II Pro resources available for specific applications. • The MFCC 8448, will succed the MFCC 8442 and 8442xD PMC as powerful computing coprocessor. It can be equipped with up to two PCC 750FX or PPC 7447 CPUs, up to 512 Mbytes of main memory, and 10-1000Mbit Ethernet. • The GPIO 8408 allows to use the power of the Virtex II Pro FPGA on a PMC without the complication of an additional processor. This is the most economic solution for applications in which the CPU of the carrier SBC board is sufficient to handle the I/O requirements. Experience acquired with the current implementation of HALs will be used in the design of these boards, to provide a hardware infrastructure which fits the software requirements as far as possible. Conclusion Commercial and military aircraft system designs face similar constraints on development time, development costs and unit system costs. With the development of a coherent ‘Lego’ of function units, CES was able to provide solutions meeting these constraints in both fields. Today, solutions originally developed for a military program are more and more frequently applied to commercial systems and vice versa.
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1000Mbit Ethernet, GPS receiver<br />
on board and a set of high-speed<br />
serial links for application specific<br />
needs.<br />
• The MFCC 8447, a successor of<br />
the MFCC 8441 and MFCC 8443<br />
is a PMC with PPC 750FX, up to<br />
256 Mbytes of main memory and<br />
most of the Virtex II Pro resources<br />
available for specific applications.<br />
• The MFCC 8448, will succed the<br />
MFCC 8442 and 8442xD PMC as<br />
powerful computing coprocessor. It<br />
can be equipped with up to two<br />
PCC 750FX or PPC 7447 CPUs, up<br />
to 512 Mbytes of main memory,<br />
and 10-1000Mbit Ethernet.<br />
• The GPIO 8408 allows to use the<br />
power of the Virtex II Pro FPGA<br />
on a PMC without the complication<br />
of an additional processor. This is<br />
the most economic solution for<br />
applications in which the CPU of<br />
the carrier SBC board is sufficient<br />
to handle the I/O requirements.<br />
Experience acquired with the current<br />
implementation of HALs will be used in<br />
the design of these boards, to provide a<br />
hardware infrastructure which fits the<br />
software requirements as far as possible.<br />
Conclusion<br />
Commercial and military aircraft system<br />
designs face similar constraints on<br />
development time, development costs and<br />
unit system costs. With the development of<br />
a coherent ‘Lego’ of function units, CES<br />
was able to provide solutions meeting<br />
these constraints in both fields. Today,<br />
solutions originally developed for a<br />
military program are more and more<br />
frequently applied to commercial systems<br />
and vice versa.