Revista PDF - Cuerpo General de Bomberos Voluntarios del Perú

CORAL TECHNICAL REQUIREMENTS DRAFT August XX, 20135.0 CORAL Compute PartitionThis section describes additional hardware and software requirements for the CORAL compute partitiondescribed by the Offer as part of Section 3.1.5.1 Compute Partition Hardware Requirements5.1.1 IEEE 754 32-Bit and 64-Bit Floating Point Numbers (TR-1)The CORAL compute node (CN) processor cores will have the ability to operate on 32-bit and64-bit IEEE 754 floating-point numbers5.1.2 Inter Core Communication (TR-1)CN cores will provide sufficient atomic capabilities along with some atomic incrementingcapabilities so that the usual higher level synchronizations (e.g., critical section or barrier) can beconstructed. These capabilities will allow the construction of memory and executionsynchronization that is extremely low latency. As the number of user threads can be large in aCORAL node, special hardware mechanisms will be provided that allow groups of threads tocoordinate collectively at a cost comparable to the cost of a memory access. Multiple groupsshould be able to synchronize concurrently. Hardware support will be provided to allow forDMA to be coherent with the local node memory. These synchronization capabilities or theirhigher-level equivalents will be directly accessible from user programs.Offer will specify the overhead, assuming no contention, of all supplied atomic instructions.5.1.3 Hardware Support for Low Overhead Threads (TR-1)The CNs will provide documented hardware mechanisms to spawn, to control and to terminatelow overhead computational threads, including a low overhead locking mechanism and a highlyefficient fetch and increment operation for memory consistency among the threads. Offeror willfully describe these mechanisms; their limitations and the potential benefit to CORALapplications for exploiting OpenMP and POSIX threads node parallelism within MPI processes.5.1.4 Hardware Interrupt (TR-2)CNs hardware will support interrupting given subsets of cores based on conditions detected bythe operating system or other cores within the subset executing the same user application.5.1.5 Hardware Performance Monitors (TR-1)The CNs will have hardware support for monitoring system performance. The hardwareperformance monitor (HPM) interface will be capable of separately counting hardware eventsgenerated by every thread executing on every core in the node. The HPM will include hardwaresupport for monitoring message passing performance and congestion on all node interconnectinterfaces of all proposed networks.The HPM will have 64b counters and the ability to notify the node OS of counter wrapping. TheHPM will support setting of counter values, saving them and restoring them, as well as readingthem in order to support sampling based on counter wrapping. The HPM will also supportinstruction-based sampling (e.g., PEBS or IBS) that tracks latencies or other data of interest inrelation to specific instructions. All HPM data will be made available directly to applicationsprogrammers and to code development tools (see section 9.2.2.9).- 22 -