VHDL Made Easy! - Xilinx
VHDL Made Easy! - Xilinx
VHDL Made Easy! - Xilinx
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32<br />
Figure 1<br />
CODING EXAMPLE 1<br />
HDL Synthesis<br />
and<br />
Built-In Clock Enables<br />
The internal flip-flops in <strong>Xilinx</strong> FPGA<br />
architectures have built-in, dedicated<br />
clock enable (CE) inputs. Appropriate use<br />
of these clock enables avoids the need for<br />
gating clocks, facilitating good synchro-<br />
always @ (posedge clk or posedge rst)<br />
begin<br />
if (rst)<br />
q
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