VHDL Made Easy! - Xilinx

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PRODUCT INFORMATION — COMPONENTS
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XC9500 CPLDs:
Managing the “Product Life Cycle”
The XC9500 CPLD family incorporates
a unique combination of product features
specifically developed to meet all the
needs for in-system programming (ISP)
throughout the entire “product life cycle.”
This product life cycle starts with boardlevel
prototyping and system debug, advances
to programming and board-level
testing during manufacturing, and finally
completes with field upgrades.
The XC9500 product features reduce
the total cost of ownership by eliminating
many of the traditional problems of product
development using PLDs. These features
include 5 V in-system programmability,
superior
pin-locking capability,
support for
10,000 program/
erase cycles, and
full 1149.1 JTAG
support for insystem
debug and
version control.
Design and
Prototyping
ISP-capable
CPLDs provide a
definite benefit
over devices requiring an external programmer.
ISP devices eliminate the handling
errors and damage associated with
removing the chip from the socket on the
circuit board.
Through the multiple design iterations
of the debug and prototyping process, the
ISP CPLD can be repeatedly reprogrammed
with different patterns while
soldered on a printed circuit board (PCB).
The ability of the architecture and tools to
support pin-locking — that is, the ability
to maintain a fixed pinout while making
logic changes internal to the device — is
crucial to avoid expensive and time-consuming
board rework. The XC9500 CPLD,
originally architected for in-system programming,
offers users the best in pinlocking
capability
Many existing ISP devices are fabricated
using traditional EEPROM technology.
However, the advanced XC9500
FastFLASHTM technology provides several
advantages over EEPROM technology.
Foremost among these is programming
endurance. EEPROM technology typicially
allows 100-1000 program/erase cycles.
FastFLASH technology has an endurance
of 10,000 program/erase cycles. This high
programming endurance minimizes or
eliminates costly board rework resulting
from reprogramming failures.
System Integration
When the entire system is assembled for
test and debug, all important logic states
should be easily accessible, and internal
logic implementations within each device
should be capable of being checked. Each
XC9500 device supports the IEEE 1149.1
boundary-scan specification, including
INTEST and USERCODE instructions used to
easily access and debug user logic and track
pattern revisions, respectively.
Manufacturing
Concurrent programming of all XC9500
CPLDs in the system with the standard
JTAG interface simplifies the manufacturing
flow in the production stage. Programming
can be done after board assembly.
This reduces production inventories,
eliminates the need for tracking multiple