ESA Document - Emits - ESA

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HMM
Assessment Study
Report: CDF-20(A)
February 2004
page 200 of 422
processing power than available using a single processor, the architecture shall evolve later
toward more distributed architectures, and possibly what is called “integrated modular avionics”
in aeronautics (standardized multi-processor platform with transparent distribution of the
functions instead of the classical allocation of processor dedicated to functions).
This last step will require the standardization of additional services to manage fault tolerance
almost transparently for applications.
3.3.6.1.6 On-board interfaces
The outcome of standardization of on-board interfaces will be a set of busses covering all the
levels of modular hardware integration. Each interconnection type is specialized and a stack of
interconnection means is necessary to guarantee functional redundance and system optimisation.
The SOIF layers will then be in charge of hiding hardware complexity at application software
level. Figure 3-55 shows the complexity as a function of bandwith. Busses already qualified for
space are shown in green.
Figure 3-55: Complexity of interconnected busses as a function of bandwith
The categories to group on-board command and data interconnecting busses are:
3.3.6.1.6.1 Chip level bus (as AMBA)