Panasonic FP Series PLC Programming Manual - CTi Automation

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Table of Contents F157 CADD Time addition ......................................... 3 − 413 P157 PCADD F158 CSUB Time substruction ...................................... 3 − 416 P158 PCSUB F159 MTRN Serial data communication P159 PMTRN for FPΣ/FP−X/FP0R .................................... 3 − 420 for FP2/FP2SH ........................................ 3 − 428 F161 MRCV Serial data reception ................................... 3 − 432 P161 PMRCV BIN arithmetic instructions F160 DSQR 32-bit data square root ................................. 3 − 435 P160 PDSQR Special instructions (High−speed counter instructions) F0 MV High−speed counter control for FP0/FP0R/FPΣ/FP−X ...... 3 − 437 Pulse output control for FP0/FP0R/FP−e/FPΣ/FP−X ....... 3 − 443 F1 DMV Writing and reading the high−speed counter and pulse output elapsed value for FP0/FP0R/FP−e/FPΣ/FP−X ............. 3 − 449 F165 CAM0 Cam control ........................................... 3 − 454 F166 HC1S Target value match on (with channel specification) ........ **** F166 HC1S Target value match on (High−speed counter control) ........ 3 − 464 F166 HC1S Target value match on (Pulse output control) .............. 3 − 467 F167 HC1R Target value match off (with channel specification) ........ **** F167 HC1R Target value match off (High−speed counter control) ........ 3 − 473 F167 HC1R Target value match off (Pulse output control) .............. 3 − 476 F168 SPD1 Positioning control (trapezoidal control) ................... 3 − 479 Positioning control (home position return) ................. 3 − 483 F169 PLS Pulse output (with channel specification)(JOG operation) .... 3 − 488 F170 PWM PWM output (with channel specification) .................. 3 − 491 F171 SPDH Pulse output (with channel specification) (trapezoidal control) ................................... 3 − 493 (home position return) ................................. 3 − 498 F171 SPDH Pulse output (trapezoidal control) ........................ 3 − 504 Pulse output (JOG positioning type 0) ..................... 3 − 511 Pulse output (JOG positioning type 1) .................... 3 − 516 F172 PLSH Pulse output (with channel specification)(JOG operation) .... 3 − 521 F172 PLSH Double word compare: Start equal Pulse output (JOG operation type 0 and 1) .......................... 3 − 525 F173 PWMH PWM output (with channel specification) ................. **** F174 SP0H Pulse output (with channel specification) (Selectable data table control operation) ................. 3 − 533 F174 SP0H Pulse output (Arbiterary data table control operation) ....... 3 − 538 CTi Automation - Phone: 800.894.0412 - Fax: 208.368.0415 - Web: www.ctiautomation.net - Email: info@ctiautomation.net xv
Page 1 and 2: CTi Automation - Phone: 800.894.041
Page 3 and 4: Table of Contents Chapter 1 Relays,
Page 5 and 6: Table of Contents 4.4.2 Operation M
Page 7 and 8: Basic Instructions Sequence basic i
Page 9 and 10: OR 16−bit data compare (OR) .....
Page 11 and 12: Control instruction Table of Conten
Page 13 and 14: Table of Contents F66 WOR 16-bit da
Page 15: Table of Contents F113 WBSL Left sh
Page 19 and 20: Table of Contents F238 DGBIN 32−b
Page 21 and 22: Table of Contents F313 F% Floating
Page 23 and 24: Table of Contents F412 POPB Restori
Page 25 and 26: Chapter 1 Relays, Memory Areas and
Page 27 and 28: 1.1 Table of Relays, Memory Areas a
Page 29 and 30: Memory Me areaa (double word) w (se
Page 31 and 32: 1.1.2 FP0R Item Number of points an
Page 33 and 34: 1.1.3 FPΣ 12k type Rel elay Memmor
Page 35 and 36: 32k type Relay ay Memmory areaa Ite
Page 37 and 38: 1.1.4 FP−X Item Number of points
Page 39 and 40: 1.1.5 FP2 1.1 Table of Relays, Memo
Page 41 and 42: 1.1.6 FP2SH 1.1 Table of Relays, Me
Page 43 and 44: 1.1.7 FP10SH 1.1 Table of Relays, M
Page 45 and 46: 1.1.8 Relay Numbers 1.1 Table of Re
Page 47 and 48: 1.1 Table of Relays, Memory Areas a
Page 49 and 50: 1.2.2 External Output Relays (Y) 1.
Page 51 and 52: 1.2 Explanation of Relays Non−hol
Page 53 and 54: 1.2.5 Link Relays (L) for FPΣ, FP
Page 55 and 56: 1.2.6 Link Relays (L) for FP2/FP2SH
Page 57 and 58: 1.2 Explanation of Relays Specifyin
Page 59 and 60: 1.2.7 Timer (T) 1.2 Explanation of
Page 61 and 62: 1.2.9 Items Shared by the Timer and
Page 63 and 64: 1.2.10 Pulse Relays (P) Note 1.2 Ex
Page 65 and 66: 1.2.11 Error Alarm Relays (E) Note
Page 67 and 68:
1.2 Explanation of Relays Clearing
Page 69 and 70:
Non−hold type data and hold−typ
Page 71 and 72:
1.3 Explanation of Memory Areas Clo
Page 73 and 74:
1.3.4 WX, WY, WR and WL 1.3 Explana
Page 75 and 76:
1.3 Explanation of Memory Areas Spe
Page 77 and 78:
1.3 Explanation of Memory Areas Ava
Page 79 and 80:
Example: Note Non−hold type Hold
Page 81 and 82:
1.3.8 Elapsed Value Area for Timer/
Page 83 and 84:
Index modification method Example 1
Page 85 and 86:
1.3.10 Index Registers (I0 to ID) (
Page 87 and 88:
1.3 Explanation of Memory Areas The
Page 89 and 90:
1.3 Explanation of Memory Areas Mod
Page 91 and 92:
Example 3: Modifying a destination
Page 93 and 94:
Modifying instruction numbers of ba
Page 95 and 96:
1.3 Explanation of Memory Areas Exa
Page 97 and 98:
1.4.2 Hexadecimal Constants (H) 1.4
Page 99 and 100:
1.4 Explanation of Constants Proces
Page 101 and 102:
1.4 Explanation of Constants Exampl
Page 103 and 104:
1.4 Explanation of Constants 1.4.4
Page 105 and 106:
1.5 Data Ranges Which can be Handle
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Chapter 2 Basic Instructions CTi Au
Page 113 and 114:
2.1 Composition of Basic Instructio
Page 115 and 116:
2.1 Composition of Basic Instructio
Page 117 and 118:
Control and subroutine instructions
Page 119 and 120:
Precautions during programming The
Page 121 and 122:
Outline AN: Connects Form A (normal
Page 123 and 124:
Basic Instructions Precautions duri
Page 125 and 126:
Explanation of example ST↑, AN↑
Page 127 and 128:
Basic Instructions Description OT
Page 129 and 130:
Outline Multiple blocks are connect
Page 131 and 132:
Outline Multiple blocks are connect
Page 133 and 134:
Basic Instructions Outline PSHS: St
Page 135 and 136:
Basic Instructions Caution regardin
Page 137 and 138:
Basic Instructions Description The
Page 139 and 140:
Basic Instructions Application exam
Page 141 and 142:
Page 143 and 144:
Basic Instructions When SET and RST
Page 146 and 147:
Basic Instructions Outline Sets the
Page 148 and 149:
Basic Instructions 4 When the value
Page 150 and 151:
Basic Instructions 2 − 40 Example
Page 152 and 153:
Basic Instructions Outline TMR:Sets
Page 154 and 155:
Page 156 and 157:
Basic Instructions Timer operation
Page 158 and 159:
Basic Instructions Outline Decremen
Page 160 and 161:
Page 162 and 163:
Basic Instructions Counter operatio
Page 164 and 165:
Basic Instructions Outline One bit
Page 166 and 167:
Basic Instructions Cautions on shif
Page 168 and 169:
Basic Instructions Description Exec
Page 170 and 171:
Page 172 and 173:
Basic Instructions You must be care
Page 174:
Basic Instructions Outline Skips to
Page 177 and 178:
Page 179 and 180:
Basic Instructions 4. When X0 is in
Page 181 and 182:
CNDE Conditional end Basic Instruct
Page 183 and 184:
EJECT Eject Outline Adds page break
Page 185 and 186:
SSTP NSTL NSTP CSTP STPE Basic Inst
Page 187 and 188:
Syntax of step ladder instruction S
Page 189 and 190:
Basic Instructions CSTP (clear step
Page 191 and 192:
The execution state (start/stop) fo
Page 193:
Basic Instructions 2 Selection bran
Page 196:
Basic Instructions Outline CALL: Ex
Page 199 and 200:
FCAL Outline Executes the specified
Page 201 and 202:
FP0/FP0R/FP−e/FPΣ/FP−X Outline
Page 203 and 204:
FP0/FP0R/FP−e/FPΣ/FP−X Basic I
Page 205 and 206:
Page 207 and 208:
FP2/FP2SH/FP10SH Outline INT: Indic
Page 209 and 210:
FP2/FP2SH/FP10SH Precautions during
Page 211 and 212:
FP2/FP2SH/FP10SH Basic Instructions
Page 213 and 214:
Page 215 and 216:
FP0/FP0R/FP−e/FPΣ/FP−X S2: Spe
Page 217 and 218:
FP0/FP0R/FP−e/FPΣ/FP−X Main pr
Page 219:
Page 222 and 223:
Basic Instructions If execution has
Page 224 and 225:
Basic Instructions Example of enabl
Page 226 and 227:
Basic Instructions Example for clea
Page 229 and 230:
FPΣ/FP−X/FP0R Basic Instructions
Page 231:
FPΣ/FP−X/FP0R 4) Header and Term
Page 235:
Page 239:
Page 243 and 244:
Page 246:
Basic Instructions Outline Performs
Page 250:
Page 254:
Page 258:
Page 262:
Page 265 and 266:
Chapter 3 High−level Instructions
Page 267 and 268:
3.1 Composition of High-level Instr
Page 269 and 270:
Page 271 and 272:
Page 274:
High−level Instructions Outline C
Page 278:
High−level Instructions F3 P3 Out
Page 284 and 285:
High−level Instructions If “0
Page 287 and 288:
Examples of hexadecimal digit copy
Page 289:
F7 P7 High−level Instructions Out
Page 293:
F10 P10 High−level Instructions O
Page 297:
FP0/FP−e F12 Outline Reads data f
Page 301:
FP2SH/FP10SH F12 P12 Outline Reads
Page 305:
FPΣ/FP−X/FP0R P13 Outline Writes
Page 311:
High−level Instructions Specifyin
Page 315:
Page 319:
F18 P18 Outline Exchanges the 16-bi
Page 323:
Page 327:
Page 331:
Page 336 and 337:
High−level Instructions Explanati
Page 339:
Page 343:
F32 P32 (P%) (%) High−level Instr
Page 347:
F34 P34 (P*W) (*W) 16-bit data mult
Page 351:
F36 P36 (PD+1) (D+1) High−level I
Page 355:
F38 High−level Instructions Outli
Page 359:
F40 (B+) 4-digit BCD data addition
Page 363:
F42 (B+) 4-digit BCD data addition
Page 367:
F45 (B−) 4-digit BCD data subtrac
Page 371:
F47 (B−) 4-digit BCD data subtrac
Page 375:
F50 (B*) 4-digit BCD data multiplic
Page 379:
F52 (B%) 4-digit BCD data division
Page 383:
F55 P55 (PB+1) (B+1) 4-digit BCD da
Page 387:
F57 (B−1) 4-digit BCD data decrem
Page 391 and 392:
F60 (CMP) P60 (PCMP) High−level I
Page 393:
High−level Instructions Precautio
Page 396 and 397:
Page 399:
F62 (WIN) P62 (PWIN) High−level I
Page 403:
F64 (BCMP) P64 (PBCMP) High−level
Page 407:
F65 (WAN) P65 (PWAN) High−level I
Page 411:
F67 (XOR) P67 (PXOR) High−level I
Page 415:
F69 (WUNI) P69 (PWUNI) High−level
Page 418 and 419:
High−level Instructions Descripti
Page 420 and 421:
High−level Instructions How to ca
Page 422 and 423:
High−level Instructions F71 (HEXA
Page 424 and 425:
High−level Instructions Conversio
Page 426 and 427:
Page 428 and 429:
High−level Instructions The conve
Page 430 and 431:
Page 432 and 433:
High−level Instructions Conversio
Page 434:
Page 437 and 438:
F75 (BINA) P75 (PBINA) High−level
Page 439 and 440:
Conversion Example The following sh
Page 441 and 442:
F76 (ABIN) P76 (PABIN) High−level
Page 443 and 444:
Example of converting an ASCII code
Page 445 and 446:
Page 447 and 448:
F78 (DABI) P78 (PDABI) High−level
Page 449 and 450:
Example of converting an ASCII code
Page 452:
High−level Instructions F81 (BIN)
Page 458:
High−level Instructions F85 (NEG)
Page 464:
High−level Instructions F89 (EXT)
Page 467:
Page 472 and 473:
High−level Instructions F92 (ENCO
Page 474:
High−level Instructions How to sp
Page 478:
High−level Instructions F94 (DIST
Page 483 and 484:
High−level Instructions 3 − 219
Page 486:
High−level Instructions F97 (DSRC
Page 490 and 491:
High−level Instructions Applicati
Page 493 and 494:
High−level Instructions Applicati
Page 496:
High−level Instructions F101 (SHL
Page 500:
High−level Instructions F103 (DSH
Page 504:
High−level Instructions F106 P106
Page 508:
High−level Instructions F109 (BIT
Page 512:
High−level Instructions F111 (WSH
Page 516:
High−level Instructions F113 (WBS
Page 520:
High−level Instructions F116 (FIF
Page 530 and 531:
High−level Instructions Measures
Page 532 and 533:
Page 534:
High−level Instructions F119 (LRS
Page 538:
High−level Instructions F120 (ROR
Page 542:
High−level Instructions F122 (RCR
Page 546:
High−level Instructions F125(DROR
Page 550:
High−level Instructions F127 (DRC
Page 554:
High−level Instructions F130 (BTS
Page 558:
High−level Instructions F132 (BTI
Page 562:
High−level Instructions F135 (BCU
Page 566 and 567:
High−level Instructions F137 (STM
Page 568 and 569:
High−level Instructions 3 If the
Page 571 and 572:
F139 High−level Instructions Outl
Page 574 and 575:
High−level Instructions F140 (STC
Page 576 and 577:
High−level Instructions F142 (WDT
Page 578 and 579:
High−level Instructions F143 (IOR
Page 580 and 581:
High−level Instructions F143 P143
Page 582:
High−level Instructions F144 Outl
Page 585 and 586:
FP0/FP−e High−level Instruction
Page 587 and 588:
FP0/FP−e Example: High−level In
Page 589:
FP2/FP2SH/FP10SH F144 High−level
Page 592 and 593:
High−level Instructions 2) Settin
Page 594 and 595:
High−level Instructions Program S
Page 596 and 597:
High−level Instructions 2) Settin
Page 598 and 599:
High−level Instructions Program W
Page 600 and 601:
High−level Instructions Specifica
Page 602 and 603:
High−level Instructions For infor
Page 604:
Page 608 and 609:
High−level Instructions The SEND
Page 610 and 611:
Page 612 and 613:
High−level Instructions Command 1
Page 614 and 615:
High−level Instructions F145 (SEN
Page 617 and 618:
(1) Specifying word unit transmissi
Page 619 and 620:
High−level Instructions Example:
Page 621 and 622:
High−level Instructions 2 Specify
Page 623 and 624:
High−level Instructions Additiona
Page 625 and 626:
FPΣ/FP−X/FP0R Specifications for
Page 627 and 628:
FPΣ/FP−X/FP0R High−level Instr
Page 629 and 630:
FPΣ/FP−X/FP0R Specifications for
Page 631 and 632:
Page 633 and 634:
Page 635 and 636:
FPΣ/FP−X/FP0R F146 (RECV) High
Page 637 and 638:
Page 639 and 640:
Page 641 and 642:
2 Example of bit unit reception Whe
Page 643 and 644:
(1) Specifying word unit reception
Page 645 and 646:
High−level Instructions Example:
Page 647 and 648:
High−level Instructions 2 Specify
Page 649 and 650:
High−level Instructions Additiona
Page 651:
Page 654:
High−level Instructions F148 (ERR
Page 657 and 658:
Specifying Slot Numbers With the FP
Page 659:
F150 (READ) Data read from intellig
Page 662:
High−level Instructions F151 (WRT
Page 665:
F152 (RMRD) Data read from MEWNET-F
Page 668 and 669:
Page 671 and 672:
High−level Instructions Specifyin
Page 673 and 674:
F155 (SMPL) P155(PSMPL) Outline Sta
Page 675 and 676:
F156 (STRG) P156(PSTRG) Outline Sto
Page 677 and 678:
F157 (CADD) P157(PCADD) High−leve
Page 680 and 681:
High−level Instructions F158 (CSU
Page 683 and 684:
High−level Instructions Usage exa
Page 686 and 687:
High−level Instructions Programmi
Page 688 and 689:
High−level Instructions Preparati
Page 690 and 691:
High−level Instructions Table of
Page 692 and 693:
High−level Instructions F159 (MTR
Page 694:
High−level Instructions 9) The co
Page 698 and 699:
High−level Instructions If nine o
Page 701:
FP0/FPΣ/FP−X/FP0R High−level I
Page 704 and 705:
High−level Instructions Program e
Page 706 and 707:
High−level Instructions High−sp
Page 709 and 710:
FP0/FP−e/FPΣ/FP−X/FP0R Program
Page 711 and 712:
FP0/FP−e/FPΣ/FP−X/FP0R Using t
Page 713:
FP0/FP−e/FPΣ/FP−X/FP0R F1 (DMV
Page 716 and 717:
High−level Instructions Table of
Page 718 and 719:
High−level Instructions F165(CAM0
Page 720 and 721:
Page 722 and 723:
High−level Instructions Example o
Page 725 and 726:
F166(HC1S) High−level Instruction
Page 728 and 729:
High−level Instructions F166(HC1S
Page 731 and 732:
FP0R F166(HC1S) High−level Instru
Page 734 and 735:
High−level Instructions F167(HC1R
Page 737 and 738:
FP0R F167(HC1R) High−level Instru
Page 740 and 741:
High−level Instructions F167(HC1R
Page 743 and 744:
FP0/FP−e 5 F168(SPD1) High−leve
Page 747 and 748:
FP0/FP−e 5 F168(SPD1) High−leve
Page 751 and 752:
FP0/FP−e High−level Instruction
Page 755:
FP0/FP−e 5 F170(PWM) High−level
Page 758 and 759:
High−level Instructions The contr
Page 762 and 763:
High−level Instructions 5 F171(SP
Page 764:
High−level Instructions For FP−
Page 768 and 769:
Page 770 and 771:
High−level Instructions Pules out
Page 772 and 773:
High−level Instructions [Explanat
Page 775 and 776:
FP0R 5 F171(SPDH) High−level Inst
Page 777 and 778:
FP0R Pulse output channels and area
Page 780 and 781:
Page 782 and 783:
High−level Instructions Setting t
Page 785 and 786:
FPΣ/FP−X F172 (PLSH) High−leve
Page 789 and 790:
FP0R 5 F172(PLSH) High−level Inst
Page 791:
FP0R (3) For deceleration, the spee
Page 794:
High−level Instructions For FP−
Page 797 and 798:
FPΣ/FP−X 5 F174(SP0H) High−lev
Page 801 and 802:
FPΣ/FP−X High−level Instructio
Page 803 and 804:
FP0R Pules output channels and area
Page 806 and 807:
Page 810 and 811:
Page 812 and 813:
Page 814 and 815:
High−level Instructions *1: Assig
Page 817:
FPΣ 5 F176(SPCH) High−level Inst
Page 821 and 822:
FP0R 5 F177(HOME) High−level Inst
Page 823:
FP0R Assignment of control code (Sp
Page 826 and 827:
Page 829:
FP-e F180 (SCR) High−level Instru
Page 833:
FP-e F182 (FILTR) High−level Inst
Page 836 and 837:
High−level Instructions Timer set
Page 838 and 839:
Page 841:
F191 (DMV3) P191 (PDMV3) High−lev
Page 845:
F216 (DOR) P216 (PDOR) High−level
Page 849:
F218(DXNR) P218(PDXNR) High−level
Page 853 and 854:
FP2/FP2SH/FP−X F230 P230 (PTMSEC)
Page 856:
Page 863:
F240(COLM) Bit line to bit column c
Page 867 and 868:
FPΣ/FP−X/FP0R 5 F250(BTOA) Outli
Page 869:
Page 873 and 874:
FPΣ/FP−X/FP0R Specifying the con
Page 875 and 876:
Page 877 and 878:
FPΣ/FP−X/FP0R 5 F252(ACHK) Outli
Page 879 and 880:
Overview of Character String Instru
Page 881:
F257 (SCMP) P257(PSCMP) High−leve
Page 885:
F259 (LEN) P259(PLEN) High−level
Page 888 and 889:
Page 891:
F262 (LEFT) P262(PLEFT) High−leve
Page 895:
F264 (MIDW) Writing a character str
Page 899:
F270(MAX) P270(PMAX) High−level I
Page 903:
F272(MIN) P272(PMIN) High−level I
Page 907:
High−level Instructions F275(MEAN
Page 911:
F277(SORT) Sort data in 16-bit data
Page 915:
F282 (SCAL) P282(PSCAL) High−leve
Page 919:
FP-e F284 (RAMP) High−level Instr
Page 923:
F286(DLIMT) P286 (PDLIMT) High−le
Page 927:
F288(DBAND) 32-bit data deadband co
Page 931:
F290(DZONE) 32-bit data zone contro
Page 935:
F301(BCOS) BCD type Cosine operatio
Page 939:
F303(BASIN) BCD type Arcsine operat
Page 943:
F305(BATAN) P305(PBATAN) High−lev
Page 947:
F310(F+) P310(PF+) High−level Ins
Page 951:
F312(F*) P312(PF*) High−level Ins
Page 955:
F314(SIN) P314(PSIN) High−level I
Page 959:
F316(TAN) P316(PTAN) High−level I
Page 963:
F318(ACOS) P318(PACOS) High−level
Page 967:
F320(LN) P320(PLN) High−level Ins
Page 971:
F322(LOG) P322(PLOG) High−level I
Page 975:
F324(FSQR) P324(PFSQR) High−level
Page 979:
F326(DFLT) P326(PDFLT) High−level
Page 983:
F328 P328(PDINT) High−level Instr
Page 987:
High−level Instructions F330(DFIX
Page 991:
High−level Instructions F332(DROF
Page 995:
High−level Instructions F334(FRIN
Page 999:
F336(FABS) P336(PFABS) High−level
Page 1003:
F338(DEG) P338(PDEG) High−level I
Page 1007:
F346(FWIN) P346(PFWIN) High−level
Page 1011:
High−level Instructions F348(FBAN
Page 1015:
Outline Searches for a maximum valu
Page 1019:
High−level Instructions F352(FMEA
Page 1023:
FP2/FP2SH/FP−X/FPΣ F354 P354 (PF
Page 1027 and 1028:
Page 1029 and 1030:
Page 1032 and 1033:
High−level Instructions 5 F356(EZ
Page 1034 and 1035:
Page 1036 and 1037:
High−level Instructions Note) Whe
Page 1038 and 1039:
Page 1040:
High−level Instructions F373(DTR)
Page 1044:
High−level Instructions F410(SETB
Page 1048:
High−level Instructions F412(POPB
Page 1052 and 1053:
Page 1054 and 1055:
Precautions Concerning Programs 4-2
Page 1056 and 1057:
Precautions Concerning Programs Ope
Page 1058 and 1059:
Precautions Concerning Programs Met
Page 1060 and 1061:
Precautions Concerning Programs 4.2
Page 1062 and 1063:
Page 1064 and 1065:
Page 1066 and 1067:
Page 1068 and 1069:
Page 1070 and 1071:
Page 1072 and 1073:
Page 1074 and 1075:
Precautions Concerning Programs Rep
Page 1076 and 1077:
Page 1078 and 1079:
Precautions Concerning Programs Out
Page 1080 and 1081:
Page 1082 and 1083:
Precautions Concerning Programs 5.
Page 1085 and 1086:
4.9 Processing During Forced Input
Page 1087 and 1088:
Operation flow diagram of FP2SH and
Page 1089 and 1090:
Chapter 5 Appendix CTi Automation -
Page 1091 and 1092:
5.1 System Registers / Special Inte
Page 1093 and 1094:
5.1.1 Table of System Registers for
Page 1095 and 1096:
Table of system registers C10, C14,
Page 1097 and 1098:
FP0 Item Input setting Address 400
Page 1099 and 1100:
FP0 Item Input setting Address 402
Page 1101 and 1102:
FP0 Item RS232C port setting Addres
Page 1103 and 1104:
5.1.2 Table of Special Internal Rel
Page 1105 and 1106:
FP0 Address Name Description R9029
Page 1107 and 1108:
Address FP0 C10, FP0 T32 C14, C16,
Page 1109 and 1110:
Page 1111 and 1112:
Page 1113 and 1114:
Page 1115 and 1116:
Page 1117 and 1118:
FP-e Highspeedcounter No. Name 400
Page 1119 and 1120:
FP-e Temperature inout No. Name 409
Page 1121 and 1122:
FP-e Relay No. Name Description R90
Page 1123 and 1124:
FP-e Relay No. Name Description R90
Page 1125 and 1126:
FP-e (A: Available, N/A: Not availa
Page 1127 and 1128:
Page 1129 and 1130:
Page 1131 and 1132:
5.1.7 Table of System Registers for
Page 1133 and 1134:
Controller input settings 1 High-sp
Page 1135 and 1136:
Tool port setting COM port setting
Page 1137 and 1138:
5.1.8 Table of Special Internal Rel
Page 1139 and 1140:
WR902 FP0R Relay No. Name Descripti
Page 1141 and 1142:
WR904 FP0R Relay No. TOOL port R904
Page 1143 and 1144:
Page 1145 and 1146:
Page 1147 and 1148:
5.1.9 Table of Special Data Registe
Page 1149 and 1150:
Address Name Description DT90022 DT
Page 1151 and 1152:
Address Name Description DT90052 Pu
Page 1153 and 1154:
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FP0R (A: Available, N/A: Not availa
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Address Name Description FP0R (A: A
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FP0R (A: Available, N/A: Not availa
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Address Name Description FP0R (A: A
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Time setting PC (PLC) link 0 settin
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Interruptinput No. Name 402 403 Pul
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No. Name Default value Descriptions
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WR901 Relay No. Name Description R9
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5.1.12 Table of Special Data Regist
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(A: Available, N/A: Not available)
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5.1.13 Table of System Registers fo
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FP-X Tr type Add- Item ress Contro
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FP-X Ry type Item Pulse I/O cassett
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FP-X Ry type Add- Item ress Contro
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FP-X Item Address Name Default valu
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FP-X Item Address Name Default valu
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5.1.14 Table of Special Internal Re
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WR902 FP-X Address Name Description
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Address Name Description DT90011 Ad
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Address Name Description DT90052 Pu
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FP-X (A: Available, N/A: Not availa
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Address Name Description FP-X (A: A
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FP-X (A: Available, N/A: Not availa
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FP-X Tr type FP-X (A: Available, N/
Page 1239 and 1240:
5.1.16 Table of System Registers fo
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Setting the number of timers and co
Page 1243 and 1244:
MEWNET-W PC link setting For PC lin
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FP2/FP2SH/FP10SH Item Address Name
Page 1247 and 1248:
FP2/FP2SH/FP10SH Add- Item ress Tim
Page 1249 and 1250:
FP2/FP2SH/FP10SH Add- Item ress MEW
Page 1251 and 1252:
Operation of DF instruction between
Page 1253 and 1254:
5.1.17 Table of Special Internal Re
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FP1/FP-M/FP2/FP2SH/FP10SH/FP3 Addre
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FP2/FP2SH/FP3/FP10SH (A: Available,
Page 1267 and 1268:
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5.2 Table of Basic Instructions Nam
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Name Boolean Symbol Description UP/
Page 1293 and 1294:
Name Boolean Symbol Description Spe
Page 1295 and 1296:
Name Boolean Symbol Description 32-
Page 1297 and 1298:
5.3 Table of High-level Instruction
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Number Name Boo-lean Ope- BCD arith
Page 1301 and 1302:
Number F76 P76 F77 P77 F78 P78 F80
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Number Name Boolean Ope- rand Desc
Page 1305 and 1306:
Number F150 P150 F151 P151 F152 P15
Page 1307 and 1308:
Number F174 F175 F176 Name Boo-lean
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Num -ber F175 F176 Name Boolean Pul
Page 1311 and 1312:
Number Name Boolean Ope- Integer ty
Page 1313 and 1314:
Number F314 P314 F315 P315 F316 P31
Page 1315 and 1316:
Number F347 P347 F348 P348 F349 P34
Page 1317 and 1318:
5.4 Table of Error codes � Differ
Page 1319 and 1320:
� Table of Syntax Check Error Err
Page 1321 and 1322:
� Table of Self-Diagnostic Error
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Error code E38 E39 Name MEWNET-F sl
Page 1325 and 1326:
Error code E43 E44 Name System watc
Page 1327 and 1328:
Error code E51 E52 E53 E54 E55 E56
Page 1329 and 1330:
Error code !64 External memory erro
Page 1331 and 1332:
5.6 Hexadecimal/Binary/BCD Decimal
Page 1333 and 1334:
5-245 CTi Automation - Phone: 800.8
Page 1335 and 1336:
Record of changes R − 2 CTi Autom
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Panasonic FP Series PLC Programming Manual - CTi Automation

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