Technical Design Report Super Fragment Separator

DRAFT
state-dependent tolerance band control). The FEC is a processor board with one operating
system (e.g. Linux). Time critical functions are implemented in FPGA technology. A
dedicated parallel bus is defined as an interface to electronics boards of devices. The FEC
provides and features a device-implemented function generator (FG) for equipment that
needs to be controlled by time-dependent functions (ramps). The FG provides linear and
quadratic interpolation at 1 MHz data rate between base points with 24 bit output resolution.
- Programmable Logic Controllers (PLCs) are increasingly used for controlling industrial
equipment. This type of controller can be chosen when the process is not synchronized to
accelerator timing and when sampling periods are longer than ~100 ms. Being highly reliable,
cost effective and easy to program via standard high-level languages, PLCs are
foreseen to manage and control vacuum components, machine cryogenics, rf monitoring,
personal safety system, interlocks, etc.
2.4.A2.3 Timing System
The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. An
important consideration in the design of the FAIR facility is a high degree of truly parallel operation
of the different machines to facilitate the different research programs.
The primary task of the timing system is to trigger and synchronize equipment actions, timed
according to the accelerator cycles, and to synchronize devices which have to operate simultaneously.
The timing system must handle 20 ms cycles (present UNILAC) as well as machine cycles
and manipulation phases in the order of several seconds for the synchrotrons and up to several
hours for the storage rings. Careful analysis of machine requirements have resulted in a two staged
timing solution: A general machine timing (GMT) system will be implemented as an event based
system. It will provide concurrency of events by transmission time compensation, event resolution
of at least 1 µs and event separation of follow-up events of better than 10 µs as well as absolute
timestamps. For high-precision synchronization beyond the parameters of the GMT (e.g. distributed
rf- and kicker-control, bunch-to-bucket transfers, time-of-flight measurements) a bunch
timing system (BuTiS) will distribute high precision clock trains (100 kHz, 200 MHz) on carefully
selected fibers, properly delayed and stabilized to compensate propagation delays to every BuTiS
end-point and achieve a timing jitter of no more than 200 ps.
The GMT will broadcast centrally generated timing telegrams in a star topology. Distribution is
based on Gigabit Ethernet transmission technology using fiber and Copper transmission lines.
Transmission rate will be 1 MHz. A dedicated bi-directional timing network is used with active
switches and fan-out modules to distribute the timing telegrams to an array of event receivers
(EVR). Upstream signal propagation allows measuring the fiber and transmission delays with
sub-microsecond precision. The emerging standard Precision Time Protocol (PTP) as defined in
IEEE 1588 is foreseen to be used to synchronize distributed clocks in the timing network and
compensate for transmission delays.
A key requirement of the FAIR control system is the need of an absolute timing reference to
timestamp the accelerator data. UTC will be adopted as the standard of date and time for all FAIR
accelerators as it is the basis for the worldwide system of civil time. The source of date and time for
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