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DRAFT<br />

Figure 2.4.139: Architecture of the accelerator control system.<br />

The FAIR control system will be implemented as an object-oriented decentralized distributed<br />

system. It will be based on a strictly modular design with well defined interfaces. This allows<br />

breaking down the project in interconnected work packages that can be implemented independently.<br />

2.4.A2.2 Hardware for Equipment Interfacing<br />

The ACS will support several ways of connecting equipment of different types. However, the<br />

number of interfaces to the ACS must be kept limited as a large variety of different interfaces<br />

cannot be supported and maintained with limited personal resources.<br />

At the resource tier, the various actuators, sensors and data acquisition devices are interfaced to the<br />

ACS through the following types of front-end controllers:<br />

- VME, PCI and emerging PCI-express single board computers are dealing with<br />

high-performance real-time processing and data acquisitions. Such systems can employ a<br />

large variety of standardized and custom I/O modules (ADC, DAC, binary I/O, Counters,<br />

etc.). Typically, the accelerator timing systems, beam diagnostic systems, and interlocks<br />

are implemented in this technology.<br />

- Most accelerator devices (e.g. all power supplies, rf-systems, kickers, etc.) are interfaced by<br />

a dedicated and cost-effective front-end controller (FEC) instead of being connected via a<br />

field-bus. This FEC is defined as the “FAIR standard controller”. It is a network node,<br />

connected to the timing network (wherever necessary), and provides local CPU-power for<br />

real-time control, fast data acquisition as well as any specific functionality needed (e.g.<br />

161

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