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DRAFT<br />

implementation for the digital interface that allows slow control and experiment data<br />

transfer from and to FEE boards already exists and is in use; the GTB-BUS a GSI development.<br />

(c) Inhomogeneous DAQ systems: From our operating experience we know, that especially<br />

the large gamma arrays come with their own customized DAQ systems. As has been seen<br />

e.g. for the RISING [85] experiments at the FRS, a certain flexibility of the host (here the<br />

NUSTAR) DAQ system is mandatory to couple these systems together. The development<br />

and implementation of the TITRIS timestamp module together with the time-ordered<br />

writing to mass storage within the MBS framework is an example for such integration<br />

efforts.<br />

Implementation: As a first step it is planned to implement a standardized front-end electronics<br />

(e.g. for the R³B/CAVEC) for fast signals. It will consist of a taquila [39] front-end board that has<br />

been developed for the upgrade of the FOPI experiment at GSI. These boards can be used to record<br />

16 channels of time-signals, amplitude- or charge-signals at a moderate channel cost of about<br />

50-60€. As interface to the detector additional FEE (e.g. [86]) boards are used, that are used to<br />

amplify, shape and split the signals prior to their input the digitizer board. Such a system can be<br />

thought of being already a replacement for a full, e.g. NIM based pre-amplifier, discriminator and<br />

CAMAC/FASTBUS based digitizer chain. The taquila boards provide also a simple time stamp<br />

mechanism. We will study the behaviour of such a system within the next two years at the<br />

R³B/CAVEC setup using the LAND neutron-detector readout as reference implementation. Further<br />

R&D steps will be accomplished to come to a fully operable FEE environment. The FEE is<br />

digitally attached via the GTB bus to a VME based processor board [87] that can be used to control<br />

the FEE readout process and to perform online data reduction (see Figure 2.4.138).<br />

Figure 2.4.138: Block diagram of the VME based SAM3 processor board. Two TMS320C6711 digital signal<br />

processors running at 100 MHz are used. It is foreseen to provide this module’s functionality within the<br />

framework of the NUSTAR DAQ system.<br />

Requests: Apart from the R³B/FAIR experiment that will be the continuation of the R³B/CAVEC<br />

156

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