An Efficient Lyapunov Equation-Based Approach for ... - Lirmm

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[17] M. D. Hill, J. R. Laurus, A. R. Lebeck et al., WARTS: Wisconsin Architectural Research Tool Set, Computer Science Department University of Wiscocnsin. [18] P. Landman and J. Rabaey, Architectural Power Analysis: The Dual Bit Type Method, IEEE Transactions on VLSI Systems, Vol.3, No.2, June 1995.
DAC'99, pages 128-133 Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses L. Benini 1 , A. Macii 2 , E. Macii 2 , M. Poncino 2 , R. Scarsi 2 1 Università di Bologna, Bologna, ITALY 40136 2 Politecnico di Torino, Torino, ITALY 10129 Abstract In this paper we present algorithms for the synthesis of encoding and decoding interface logic that minimizes the average number of transitions on heavily-loaded global bus lines. The approach automatically constructs low-transition activity codes and hardware implementation of encoders and decoders, given information on word-level statistics. We present an accurate method that is applicable to low-width buses, as well as approximate methods that scale well with bus width. Furthermore, we introduce an adaptive architecture that automatically adjusts encoding to reduce transition activity on buses whose word-level statistics are not known apriori. Experimental results demonstrate that our approach well outperforms low-power encoding schemes presented in the past. References [1] M. R. Stan, W. P. Burleson, “Bus-Invert Coding for Low-Power I/O," [2] L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Address Bus Encoding Techniques for System-Level Power Optimization," DATE-98, pp. 861-866, Feb. 1998. [3] E. Musoll, T. Lang, J. Cortadella, “Working-Zone Encoding for Reducing the Energy in Microprocessor Address Buses," IEEE Trans. on VLSI Systems, Vol. 6, No. 4, pp. 568-572, Dec. 1998. [4] M. R. Stan, W. P. Burleson, “Low-Power Encodings for Global Communication in CMOS VLSI," IEEE Trans. on VLSI Systems, Vol. 5 No. 4, pp. 444-455, Dec. 1997. [5] H. Mehta, R. M. Owens, M. J. Irwin, “Some Issues in Gray Code Addressing," GLS-VLSI-96, pp. 178-180, Mar. 1996. [6] L. Benini G. De Micheli, E. Macii, M. Poncino, S. Quer, “Reducing Power Consumption of Core-Based Systems By Address Bus Encoding", IEEE Trans. on VLSI Systems, Vol. 6, No. 4, pp. 554-562, Dec. 1998. [7] S. Ramprasad, N. R. Shanbhag, I. N. Hajj, “Achievable Bounds on sIgnal Transition Activity," ICCAD-97, pp. 126-131, Nov. 1997. [8] S. Ramprasad, N. R. Shanbhag, I. N. Hajj, “Signal Coding for Low Power: Fundamental Limits and Practical Realizations," ISCAS-98, pp. 1-4, Jun. 1998.
Page 1 and 2: DAC'99, pages 1-6 An Efficient Lyap
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Page 7 and 8: [21] P. W. Purdom and C. A. Brown.
Page 9 and 10: [16] F. Somenzi. CUDD: CU Decision
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Page 31 and 32: [74] T.E. Williams. Self-Timed Ring
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[19] G. Karypis and V. Kumar. Multi
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[15] S. Dutt and W. Deng, “VLSI C
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[15] B. Landman and R. Russo, “On
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DAC'99, pages 367-372 An a-approxim
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DAC'99, pages 379-384 Automated Pha
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DAC'99, pages 385-390 Enhancing Sim
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DAC'99, pages 391-396 Cycle-based S
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DAC'99, pages 397-401 Exploiting Po
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DAC'99, pages 402-407 Formal Verifi
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DAC'99, pages 414-419 A Framework f
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DAC'99, pages 420-424 Fast Prototyp
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DAC'99, pages 436-441 Stand-by Powe
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DAC'99, pages 446-451 A Practical G
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[15] A. R. Conn, L. N. Vicente, and
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DAC'99, pages 466-471 Wave Steering
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[WM89] W.S. Wong, and R.J.T. Morris
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[18] L. P. P. P. van Ginneken, “B
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[18] C.M. Kyung et al., “HK386: A
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[14] A. Casotto, ed., Octtools-5.1
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DAC'99, pages 502-506 Noise-aware R
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DAC'99, pages 511-516 ECL: A Specif
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DAC'99, pages 523-528 Vex - A CAD t
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DAC'99, pages 535-536 Panel: MEMS C
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DAC'99, pages 543-548 Efficient Cap
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[14] K. J. Kerns and A. T. Yang,
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[17] C.-H. Hwang and A. Wu, “A Pr
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DAC'99, pages 568-573 Low-Power Beh
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DAC'99, pages 574-579 A Methodology
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DAC'99, pages 586-591 Microprocesso
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[16] J. P. Bergmann and M. A. Horow
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DAC'99, pages 604-609 Engineering C
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DAC'99, pages 610-615 Reconfigurabl
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[16] R. Niemann and P. Marwedel,
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DAC'99, pages 629-634 Multi-Time Si
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DAC'99, pages 635-640 Efficient com
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DAC'99, pages 647-652 Test Generati
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[20] I. Pomeranz and S.M. Reddy “
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DAC'99, pages 666-671 Simulation Ve
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DAC'99, pages 672-677 A Two-State M
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DAC'99, pages 684-690 A Massively-P
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DAC'99, pages 691-696 Dynamic Fault
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[18] A.W. Roscoe, C. A. R. Hoare.
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DAC'99, pages 709-714 SOI Digital C
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DAC'99, pages 715-720 Equivalent El
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DAC'99, pages 721-724 Effects of In
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DAC'99, pages 731-736 Functional Ti
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DAC'99, pages 742-747 On ILP Formul
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DAC'99, pages 754-759 Built-In Test
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DAC'99, pages 766-771 A Floorplan-b
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[18] Ramesh Harjani and Tom Lee,
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DAC'99, pages 784-789 Hardware Reus
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DAC'99, pages 794-797 Java Driven C
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DAC'99, pages 799-804 Subwavelength
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DAC'99, pages 805-810 Synthesis of
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DAC'99, pages 817-822 Constraint Dr
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DAC'99, pages 827-830 SOFTWARE ENVI
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[18] B. Schneier, 1963- Applied Cry
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DAC'99, pages 843-848 Effective Ite
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DAC'99, pages 849-854 Behavioral Sy
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DAC'99, pages 861-866 Design Consid
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DAC'99, pages 879-884 A CAD Tool fo
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[18] W. R. Hunter, “Self-consiste
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DAC'99, pages 898-903 A Framework f
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DAC'99, pages 910-914 Interconnect
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DAC'99, pages 915-920 IC Analyses I
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DAC'99, pages 927-932 A Methodology
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DAC'99, pages 939-944 Exploiting In
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[20] S. Kirkpatrick, C.D. Gelatt, M
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[16] D. Leenaerts, “Application o
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DAC'99, pages 964-969 Cycle and Pha
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DAC'99, pages 970-975 A Study in Co
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[16] H. Sarin, and A. McNelly, “A
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[15] H.M. Greenhouse, “Design of
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DAC'99, pages 994-998 Optimization
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