An Efficient Lyapunov Equation-Based Approach for ... - Lirmm
An Efficient Lyapunov Equation-Based Approach for ... - Lirmm
An Efficient Lyapunov Equation-Based Approach for ... - Lirmm
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
DAC'99, pages 68-71<br />
Gate-Level Design Exploiting Dual Supply Voltages <strong>for</strong> Power-Driven Applications<br />
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang*, Wen-Bone Jone*<br />
EE & *CS, Nat’l Chung-Cheng Univ., Chiayi 621, Taiwan, ROC<br />
Abstract<br />
The advent of portable and high-density devices has made power consumption a critical design<br />
concern. In this paper, we address the problem of reducing power consumption via gate-level<br />
voltage scaling <strong>for</strong> those designs that are not under the strictest timing budget. We first use a<br />
maximum-weighted independent set <strong>for</strong>mulation <strong>for</strong> voltage reduction on non-critical part of the<br />
circuit. Then, we use a minimum-weighted separator set <strong>for</strong>mulation to do gate sizing and<br />
integrate the sizing procedure with a voltage scaling procedure to enhance power saving on the<br />
whole circuit. The proposed methods are evaluated using the MCNC benchmark circuits. and an<br />
average of 19.12% power reduction over the circuits having only one supply voltage has been<br />
achieved.<br />
References<br />
[1] A. P. Chandrakasan and R. W. Brodersen, Low-power CMOS digital design, Kluwer Academic Publishers, 1995.<br />
[2] T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Algorithms, Chap. 27, MIT Press, McGraw-Hill Book Co.,<br />
1992.<br />
[3] D. Kagaris and S. Tragoudas, ”Maximum independent sets on transitive graphs and their applications in testing<br />
and CAD,” Proc. Int. Conf. on Computer-Aided Design, Nov. 1997. pp. 736-740,<br />
[4] S. Raje and M. Sarrafzadeh, ”Variable voltage scheduling,” Int. Symp. on Low Power Design, 1995, pp. 9-14.<br />
[5] J. D. Meindl, ”Low power microelectronics: retrospect and prospect,” Proc. IEEE, vol. 83, no. 4, Apr. 1995.<br />
[6] E. M. Sentovich et al, ”SIS : A System <strong>for</strong> Sequential Circuit Synthesis,” Technical report UCB/ERL M92/41,<br />
Univ. of Cali<strong>for</strong>nia, Berkeley, May 1992.<br />
[7] D. Singh et al., ”Power conscious CAD tools and methodologies: a perspective,” Proc. IEEE, vol. 83, no. 4, Apr.<br />
1995, pp. 570-593.<br />
[8] K. Usami and M. Horowitz, ”Clustered voltage scaling technique <strong>for</strong> low-power design” Int. Symp. on Low<br />
Power Design, 1995, pp. 3-8.<br />
[9] K. Usami et al., ”Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media<br />
Processor” IEEE J. Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 463-472.<br />
[10] Wang, J. S., Shieh, S. J., Wang, J. C., and Yeh, C. Design of standard cells used in low power ASICs exploiting<br />
multiple-supply-voltage scheme. Proc. 11th ASIC Conf., Sept. 1998.