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[12] L. Benini and G. De Micheli, Dynamic Power Management: Design Techniques and CAD Tools, Kluwer Academic Publishers, Norwell, MA, 1997. [13] A. Chatterjee and R. K. Roy, “Synthesis of low power DSP circuits using activity metrics,” in Proc. Intl. Conf. VLSI Design, pp. 255–270, Jan. 1994. [14] G. Lakshminarayana and N. K. Jha, “FACT: A framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions,” in Proc. Design Automation Conf., pp. 102–107, June 1998. [15] OpenCAD V 5 Users Manual, NEC Electronics, Inc., Sept. 1997.
DAC'99, pages 62-67 Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-Based Designs Chingwei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang EE Dept., Nat’l Chung-Cheng Univ., Chiayi 621, Taiwan, ROC Abstract Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous researches focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this paper, we present the layout techniques that feasiblize the approach in cell-based design environment. A new block layout style is proposed to support the voltage scaling with conventional standard cell libraries. The block layout can be automatically generated via a simulated annealing based placement algorithm. In addition, we propose a new cell layout style with built-in multiple supply rails. Using the cell layout, gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques produce very promising results. References [1] Chandrakasan, A. P. and Brodersen, R. W. Low-power CMOS digital design. Kluwer Academic Publishers, 1995. [2] Chang, J. M. and Pedram, M. Energy minimization using multiple supply voltages. Proc. 1996 Int. Symp. on Low Power Electronics and Design, pp. 157-162, 1996. [3] Kirkpatrick, S. et. al., Optimization by Simulated Annealing. Science, Vol. 220, May 1983, pp. 671-680. [4] Raje, S. and Sarrafzadeh, M. Variable voltage scheduling. Int. Symp. on Low Power Design, 1995, pp. 9-14. [5] Deng, C. Power analysis for CMOS/BiCMOS circuits. Proc. Int. Workshop on Low Power Design, Apr. 1994, pp. 3-8. [6] Johnson, M. C. and Roy, K. Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints. Proc. Int. Conf. on Computer Design, pp. 72-77, 1996. [7] Johnson, M. C. and Roy, K. Scheduling and optimal voltage selection for low power multi-voltage DSP datapaths. Proc. Int. Symp. on Circuits and Systems, vol. 3, pp. 2152-2155, 1997. [8] Sechen, C. et al., TimberWolf: mixed macro/standard cell floorplanning, placement, and routing package. Yale University, May 1, 1992. [9] Usami, K. and Horowitz, M. Clustered voltage scaling technique for low-power design. Int. Symp. on Low Power Design, 1995, pp. 3-8. [10] Usami, K. et al. Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor. IEEE J. Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 463-472. [11] Uehara, T. and van Cleemput, W. M. Optimal layout of CMOS functional arrays. IEEE Trans. Comput., vol. C- 30, pp. 305-312, May 1981. [12] Chang, M. C., Master Thesis, EE Dept., Nat’l Chung-Cheng Univ., Jul. 1997.
Page 1 and 2: DAC'99, pages 1-6 An Efficient Lyap
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DAC'99, pages 268-273 An O-Tree Rep
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DAC'99, pages 280-285 Genetic List
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[19] M. Potkonjak and J. Rabaey,
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DAC'99, pages 296-299 A Reordering
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DAC'99, pages 306-311 Improving Sym
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DAC'99, pages 317-320 Symbolic Mode
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DAC'99, pages 321-326 Power Efficie
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DAC'99, pages 327-332 Global Multim
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DAC'99, pages 333-336 Implementatio
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DAC'99, pages 341-342 Panel: Cell L
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[19] G. Karypis and V. Kumar. Multi
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[15] S. Dutt and W. Deng, “VLSI C
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[15] B. Landman and R. Russo, “On
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DAC'99, pages 367-372 An a-approxim
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DAC'99, pages 379-384 Automated Pha
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DAC'99, pages 385-390 Enhancing Sim
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DAC'99, pages 391-396 Cycle-based S
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DAC'99, pages 397-401 Exploiting Po
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DAC'99, pages 402-407 Formal Verifi
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DAC'99, pages 414-419 A Framework f
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DAC'99, pages 420-424 Fast Prototyp
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DAC'99, page 429 Panel: Parasitic E
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DAC'99, pages 436-441 Stand-by Powe
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DAC'99, pages 446-451 A Practical G
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[15] A. R. Conn, L. N. Vicente, and
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DAC'99, pages 466-471 Wave Steering
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[WM89] W.S. Wong, and R.J.T. Morris
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[18] L. P. P. P. van Ginneken, “B
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[18] C.M. Kyung et al., “HK386: A
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[14] A. Casotto, ed., Octtools-5.1
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DAC'99, pages 502-506 Noise-aware R
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DAC'99, pages 511-516 ECL: A Specif
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DAC'99, pages 523-528 Vex - A CAD t
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DAC'99, pages 535-536 Panel: MEMS C
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DAC'99, pages 543-548 Efficient Cap
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[14] K. J. Kerns and A. T. Yang,
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[17] C.-H. Hwang and A. Wu, “A Pr
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DAC'99, pages 568-573 Low-Power Beh
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DAC'99, pages 574-579 A Methodology
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DAC'99, pages 586-591 Microprocesso
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[16] J. P. Bergmann and M. A. Horow
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DAC'99, pages 604-609 Engineering C
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DAC'99, pages 610-615 Reconfigurabl
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[16] R. Niemann and P. Marwedel,
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DAC'99, pages 629-634 Multi-Time Si
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DAC'99, pages 635-640 Efficient com
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DAC'99, pages 647-652 Test Generati
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[20] I. Pomeranz and S.M. Reddy “
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DAC'99, pages 666-671 Simulation Ve
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DAC'99, pages 672-677 A Two-State M
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DAC'99, pages 684-690 A Massively-P
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DAC'99, pages 691-696 Dynamic Fault
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[18] A.W. Roscoe, C. A. R. Hoare.
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DAC'99, pages 709-714 SOI Digital C
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DAC'99, pages 715-720 Equivalent El
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DAC'99, pages 721-724 Effects of In
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DAC'99, pages 731-736 Functional Ti
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DAC'99, pages 742-747 On ILP Formul
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DAC'99, pages 754-759 Built-In Test
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DAC'99, pages 766-771 A Floorplan-b
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[18] Ramesh Harjani and Tom Lee,
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DAC'99, pages 784-789 Hardware Reus
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DAC'99, pages 794-797 Java Driven C
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DAC'99, pages 799-804 Subwavelength
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DAC'99, pages 805-810 Synthesis of
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DAC'99, pages 817-822 Constraint Dr
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DAC'99, pages 827-830 SOFTWARE ENVI
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[18] B. Schneier, 1963- Applied Cry
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DAC'99, pages 843-848 Effective Ite
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DAC'99, pages 849-854 Behavioral Sy
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DAC'99, pages 861-866 Design Consid
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DAC'99, pages 867-872 Cycle-Accurat
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DAC'99, pages 879-884 A CAD Tool fo
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[18] W. R. Hunter, “Self-consiste
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DAC'99, pages 898-903 A Framework f
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DAC'99, pages 910-914 Interconnect
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DAC'99, pages 915-920 IC Analyses I
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DAC'99, pages 927-932 A Methodology
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DAC'99, pages 939-944 Exploiting In
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[20] S. Kirkpatrick, C.D. Gelatt, M
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[16] D. Leenaerts, “Application o
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DAC'99, pages 964-969 Cycle and Pha
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DAC'99, pages 970-975 A Study in Co
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[16] H. Sarin, and A. McNelly, “A
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[15] H.M. Greenhouse, “Design of
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DAC'99, pages 994-998 Optimization
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