using the bootstrap loader

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CONFIGURING THE FIRST STAGE 3.2.3 %AUTO CONFIGURE MEMORY Macro (MULTIBUS® II Only) - - You should include the %AUTO _CONFIGURE_MEMORY macro only for MULTIBUS II systems, and only for those systems in which the Bootstrap Loader is invoked upon system reset (as opposed to under program control). In systems that include the monitor in PROM devices, the monitor becomes active before the Bootstrap Loader, and it should invoke its own %AUTO _ CONFIGURE_MEMORY macro. Therefore, invoking the macro from the Bootstrap Loader is unnecessary. The syntax of the macro is where: %AUTO _ CONFIGURE _ MEMO RY(interface _ type [,start_address]) interface _ type A string representing the bus interface of the memory board( s) to be configured. Valid strings are LBX, PSB, orLBX+PSB. start address The starting 64K page of memory when PSB memory is being configured. Three possible configuration options exist: iLBX only, iPSB only, or iLBX and iPSB. You must specify the required parameters using one of the following three methods: %AUTO _ CONFIGURE_MEMORY (LBX) This option configures memory boards accessible to the processor via the iLBX bus. Using this configuration option, the macro assigns sequential consecutive addresses beginning with zero for the start and stop addresses of each iLBX memory board. Board configuration proceeds from the board occupying the lowest slot number to the board occupying the highest slot number. %AUTO _ CONFIGURE_MEMORY (PSB, start address) This option configures memory boards accessible to the CPU via the iPSB bus. Using this configuration option, the macro assigns sequential consecutive addresses for the start and stop addresses of each iPSB memory board. The assigned addresses begin with the supplied starting address. Board configuration proceeds from the board occupying the lowest slot number to the board occupying the highest slot number. %AUTO _ CONFIGURE_MEMORY (LBX + PSB) This option configures memory in the same manner as the first option, with one additional configuration. All boards on the iLBX bus that also have iPSB interfaces have the same starting and ending addresses for both interfaces. Bootstrap Loader 3-11
CONFIGURING THE FIRST STAGE The following syntax errors can occur if you enter incorrect parameters or incorrect combinations of parameters. ERROR - , invalid interface type ERROR - invalid parameter combination 3.2.4 %CPU Macro The %CPU macro identifies the type of CPU that executes the bootstrap loading operation. You must include this macro in the BS1.A86 or BS1MB2.A86 file once (and only once). The syntax of the CPU macro is where: %CPU( cpu type) The type of CPU executing the bootstrap operation. Valid types are: Type 8086 8088 80186 80188 80286 80386 Description 8086 processor (iRMX I only) 8088 processor (iRMX I only) 80186 processor (iRMX I only) 80188 processor (iRMX I only) 80286 processor (iRMX I and iRMX II) 386® processor (iRMX I and iRMX II) 3.2.5 %BMPS Macro (MULTIBUS® II Only) 3-12 The %BMPS macro configures the message passing system used during bootstrap loading. This macro identifies the base address of the Message Passing Coprocessor (MPC), address distance between MPC ports, and information that defines how direct memory access (DMA) transfers occur. If you have a MULTIBUS II system that bootloads from a device whose driver uses MULTIBUS II transport protocol (i.e. the 186/224A driver), you must use this macro. If you have a MUL TIBUS I system or a system that bootloads from a device whose driver does not use MUL TIBUS II transport protocol, you must not use this macro. The syntax of the %BMPS macro is %BMPS (mpc$base$addr, port$sep, duty$cycle, dma$base$addr, dma$in, dma$out, dma$trans, data$width) Bootstrap Loader
Page 2: iRMX® Bootstrap loader Reference M
Page 5 and 6: I \
Page 7 and 8: PREFACE Appendix B This appendix de
Page 9 and 10: Contents Chapter 3. Configuring the
Page 11 and 12: Contents Chapter 6. Writing a Custo
Page 14 and 15: 1.1 INTRODUCTION OVERVIEW OF BOOTST
Page 16 and 17: 1.2 THE STAGES OF THE BOOTSTRAP LOA
Page 18 and 19: Generic Third Stage OVERVIEW OF BOO
Page 20 and 21: OVERVIEW OF BOOTSTRAP LOADER OPERAT
Page 22 and 23: * OVERVIEW OF BOOTSTRAP LOADER OPER
Page 24: OVERVIEW OF BOOTSTRAP LOADER OPERAT
Page 27 and 28: USING THE BOOTSTRAP LOADER 2-2 When
Page 29 and 30: USING THE BOOTSTRAP LOADER 2-4 For
Page 31 and 32: USING THE BOOTSTRAP LOADER 2-6 Alth
Page 33 and 34: USING THE BOOTSTRAP LOADER * 2-8 NO
Page 35 and 36: CONFIGURING THE FIRST STAGE 3.1.1 F
Page 37 and 38: CONFIGURING THE FIRST STAGE 3-4 nam
Page 39: CONFIGURING THE FIRST STAGE 3-6 , ,
Page 42 and 43: CONFIGURING THE FIRST STAGE The ord
Page 46 and 47: where: mpc$base$addr port$sep duty$
Page 48 and 49: 3.2.7 %CONSOLE, %MANUAL, and %AUTO
Page 50 and 51: CONFIGURING THE FIRST STAGE • If
Page 52 and 53: The syntax of this macro is %CLEAR
Page 54 and 55: The syntax of the %SERIAL _ CHANNEL
Page 56 and 57: CONFIGURING THE FIRST STAGE flags A
Page 58 and 59: The syntax of the %DEVICE macro is
Page 60 and 61: CONFIGURING THE FIRST STAGE Table 3
Page 62 and 63: 3.3 BSERR.A86 CONFIGURATION FILE CO
Page 64 and 65: 3.3.4 %AGAIN Macro CONFIGURING THE
Page 66 and 67: 3.4 DEVICE DRIVER CONFIGURATION FIL
Page 68 and 69: In the BMSC.A86 file, the default i
Page 71 and 72: CONFIGURING THE FIRST STAGE 3.4.6 %
Page 73 and 74: CONFIGURING THE FIRST STAGE def cla
Page 75 and 76: CONFIGURING THE FIRST STAGE In the
Page 77 and 78: CONFIGURING THE FIRST STAGE 3.4.11
Page 79 and 80: CONFIGURING THE FIRST STAGE 3-46 Mu
Page 82: The format for invoking the submit
Page 85 and 86: CONFIGURING THE THIRD STAGE 4.2 OVE
Page 87 and 88: CONFIGURING THE THIRD STAGE 4.3 BS3
Page 89 and 90: CONFIGURING THE THIRD STAGE name bs
Page 91 and 92: CONFIGURING THE THIRD STAGE 4.3.1 %
Page 93 and 94: CONFIGURING THE THIRD STAGE Table 4
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CONFIGURING THE THIRD STAGE The def
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CONFIGURING THE THIRD STAGE This ma
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attachfile bsl as :fl: asm86 bg3.a8
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Generic third stage where: SUBMIT B
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5.1 INTRODUCTION 5 WRITING A CUSTOM
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5.2 DEVICE INITIALIZE PROCEDURE WRI
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Adding the following statements acc
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", ", """""", " " , " " "", " """""
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WRITING A CUSTOM FIRST-STAGE DRIVER
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Condition Codes E$OK BS$E$BUFFER$SI
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Output Parameter exception$ptr Desc
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Condition Codes E$OK BS$E$TRANSMISS
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END CODE; END SAMPLE_BS$RECEIVE; Co
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WRITING A CUSTOM THIRD-STAGE DRIVER
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7.1 INTRODUCTION ERROR HANDLING 7 I
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ERROR HANDLING 7-4 Error Code: 13 D
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ERROR HANDLING Table 7-1. Postmorte
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A.1 INTRODUCTION AUTOMATIC A BOOT D
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AUTOMATIC BOOT DEVICE RECOGNITION A
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AUTOMATIC BOOT DEVICE RECOGNITION (
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PROMMING THE BOOTSTRAP B LOADER AND
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C.1 OVERVIEW D-MON386 MONITOR C Int
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%Again 3-29, 3-31 %Auto 3-15 %Auto
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BS$SEND 5-18, 5-19 BS$SEND$RSVP 5-1
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E Editing BSl.A86 3-8, 5-38 Error c
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Intel-supplied first stage drivers
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Send transition model 5-18 Serial c
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INTEL CORPORATION 3065 Bowers Avenu
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