using the bootstrap loader

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CONFIGURING THE FIRST STAGE The order in which the macros should appear is the same order that they are listed in the BS l.A86 or BS IMB2.A86 file. The following sections describe the macros that can appear in the BS1.A86 and BS IMB2.A86 files. Because the Bootstrap Loader supports both iRMX I and iRMX II Operating Systems, some of these macros apply to one Operating System and not the other. In such cases, the section heading notes the operating system to which the macro applies. When no operating system designation appears, the macro is valid for both the iRMX I and iRMX II Operating Systems. The macros are described in the order they are listed in the BS l.A86 and BS IMB2.A86 files. If you make a syntax error when entering macros into the BS l.A86 or BS IMB2.A86 file, an error message appears when assembling the file. For example, if you misspell a macro name in a macro call, the following type of message may be returned: *** ERROR #301 IN 129, (MACRO) UNDEFINED MACRO NAME INSIDE CALL: BAD NAME *** _______________________________ t *** ERROR #1 IN 129, SYNTAX ERROR If an error such as this occurs, check for correctness in the BS l.A86 or BS IMB2.A86 file and attempt to reassemble the file. 3.2.1 %BI5T Macro (MUL TIBU5® II Only) MULTIBUS II systems include a Built-In Self Test (BIST) program in PROM devices that verifies MUL TIBUS II hardware when the hardware is powered up. The %BIST macro causes the Bootstrap Loader to invoke the BIST program on the CPU board during Bootstrap Loader initialization. The BIST program then tests the hardware. If the BIST program finds an error condition, it places an error code in the AX register and loops. It does not call the Bootstrap Loader's BSERROR routine because an error of this type implies that the system hardware is inoperable. The %BIST macro should be included only for MUL TIBUS II systems, and only for those systems that don't also include a monitor in PROM devices. In systems that include a monitor, the monitor becomes active before the Bootstrap Loader, and it invokes the BIST program. Therefore, invoking the BIST program from the Bootstrap Loader is unnecessary. Bootstrap Loader 3-9
CONFIGURING THE FIRST STAGE The syntax of the macro is where: %BIST ( address) address Address of the CPU board's BIST program. This parameter must be entered in the form BASE:OFFSET (for example, 1234:5678). To determine the address of your CPU board's BIST program, refer to the hardware reference manual for that board. 3.2.2 %COPV Macro (MULTIBUS® II Only) 3-10 The %COPY macro is used with 386/116- and 386/120-based systems. If your system is not of this type, do not include the %COPY macro in the BS 1MB2.A86 file. Both iSBC 386/116- and iSBC 386/120-based systems locate EPROM memory at the top of the 4 gigabyte address space supported by the 803861101 upon reset. However, the first stage of the Bootstrap Loader must execute within the first megabyte of address space (real mode). Because the first stage must be repositioned within memory, you must use the %COPY macro for any application where the EPROM memory is mapped outside of the first megabyte of address space upon reset. In contrast, the iSBC 386/2X and iSBC 386/3X systems locate EPROM memory at the top of the first megabyte of memory space upon reset. Thus, the %COPY macro is unnecessary. This macro copies the first stage of the Bootstrap Loader from EPROM devices to the low megabyte of RAM. You should only specify this macro if you do not have a monitor installed and the Bootstrap loader executes first upon system reset. The syntax of the %COPY macro is as follows: where: src 10 src hi dest 10 dest hi count 10 count hi The low word of the 24-bit physical source address. The high byte of the 24-bit physical source address. The low word of the 24-bit physical destination address. The high byte of the 24-bit physical destination address. The low word of the number of bytes in the first stage. The high byte of the number of bytes in the first stage. Bootstrap Loader
Page 2: iRMX® Bootstrap loader Reference M
Page 5 and 6: I \
Page 7 and 8: PREFACE Appendix B This appendix de
Page 9 and 10: Contents Chapter 3. Configuring the
Page 11 and 12: Contents Chapter 6. Writing a Custo
Page 14 and 15: 1.1 INTRODUCTION OVERVIEW OF BOOTST
Page 16 and 17: 1.2 THE STAGES OF THE BOOTSTRAP LOA
Page 18 and 19: Generic Third Stage OVERVIEW OF BOO
Page 20 and 21: OVERVIEW OF BOOTSTRAP LOADER OPERAT
Page 22 and 23: * OVERVIEW OF BOOTSTRAP LOADER OPER
Page 24: OVERVIEW OF BOOTSTRAP LOADER OPERAT
Page 27 and 28: USING THE BOOTSTRAP LOADER 2-2 When
Page 29 and 30: USING THE BOOTSTRAP LOADER 2-4 For
Page 31 and 32: USING THE BOOTSTRAP LOADER 2-6 Alth
Page 33 and 34: USING THE BOOTSTRAP LOADER * 2-8 NO
Page 35 and 36: CONFIGURING THE FIRST STAGE 3.1.1 F
Page 37 and 38: CONFIGURING THE FIRST STAGE 3-4 nam
Page 39: CONFIGURING THE FIRST STAGE 3-6 , ,
Page 44 and 45: CONFIGURING THE FIRST STAGE 3.2.3 %
Page 46 and 47: where: mpc$base$addr port$sep duty$
Page 48 and 49: 3.2.7 %CONSOLE, %MANUAL, and %AUTO
Page 50 and 51: CONFIGURING THE FIRST STAGE • If
Page 52 and 53: The syntax of this macro is %CLEAR
Page 54 and 55: The syntax of the %SERIAL _ CHANNEL
Page 56 and 57: CONFIGURING THE FIRST STAGE flags A
Page 58 and 59: The syntax of the %DEVICE macro is
Page 60 and 61: CONFIGURING THE FIRST STAGE Table 3
Page 62 and 63: 3.3 BSERR.A86 CONFIGURATION FILE CO
Page 64 and 65: 3.3.4 %AGAIN Macro CONFIGURING THE
Page 66 and 67: 3.4 DEVICE DRIVER CONFIGURATION FIL
Page 68 and 69: In the BMSC.A86 file, the default i
Page 71 and 72: CONFIGURING THE FIRST STAGE 3.4.6 %
Page 73 and 74: CONFIGURING THE FIRST STAGE def cla
Page 75 and 76: CONFIGURING THE FIRST STAGE In the
Page 77 and 78: CONFIGURING THE FIRST STAGE 3.4.11
Page 79 and 80: CONFIGURING THE FIRST STAGE 3-46 Mu
Page 82: The format for invoking the submit
Page 85 and 86: CONFIGURING THE THIRD STAGE 4.2 OVE
Page 87 and 88: CONFIGURING THE THIRD STAGE 4.3 BS3
Page 89 and 90: CONFIGURING THE THIRD STAGE name bs
Page 91 and 92: CONFIGURING THE THIRD STAGE 4.3.1 %
Page 93 and 94:
CONFIGURING THE THIRD STAGE Table 4
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CONFIGURING THE THIRD STAGE The def
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CONFIGURING THE THIRD STAGE This ma
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attachfile bsl as :fl: asm86 bg3.a8
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Generic third stage where: SUBMIT B
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5.1 INTRODUCTION 5 WRITING A CUSTOM
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5.2 DEVICE INITIALIZE PROCEDURE WRI
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Adding the following statements acc
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", ", """""", " " , " " "", " """""
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WRITING A CUSTOM FIRST-STAGE DRIVER
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Condition Codes E$OK BS$E$BUFFER$SI
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Output Parameter exception$ptr Desc
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Condition Codes E$OK BS$E$TRANSMISS
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END CODE; END SAMPLE_BS$RECEIVE; Co
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WRITING A CUSTOM THIRD-STAGE DRIVER
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7.1 INTRODUCTION ERROR HANDLING 7 I
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ERROR HANDLING 7-4 Error Code: 13 D
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ERROR HANDLING Table 7-1. Postmorte
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A.1 INTRODUCTION AUTOMATIC A BOOT D
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AUTOMATIC BOOT DEVICE RECOGNITION A
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AUTOMATIC BOOT DEVICE RECOGNITION (
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PROMMING THE BOOTSTRAP B LOADER AND
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C.1 OVERVIEW D-MON386 MONITOR C Int
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%Again 3-29, 3-31 %Auto 3-15 %Auto
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BS$SEND 5-18, 5-19 BS$SEND$RSVP 5-1
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E Editing BSl.A86 3-8, 5-38 Error c
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Intel-supplied first stage drivers
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Send transition model 5-18 Serial c
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INTEL CORPORATION 3065 Bowers Avenu
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