3D Charge Trapping NAND Flash Memory - Sematech
3D Charge Trapping NAND Flash Memory - Sematech
3D Charge Trapping NAND Flash Memory - Sematech
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<strong>3D</strong> <strong>Charge</strong> <strong>Trapping</strong> (CT) <strong>NAND</strong> <strong>Flash</strong><br />
Yen-Hao Shih<br />
Macronix International Co., Ltd.<br />
Hsinchu, Hsinchu,<br />
Taiwan<br />
Email: yhshih@mxic.com.tw<br />
1
Outline<br />
� Why Does <strong>NAND</strong> Go to <strong>3D</strong>?<br />
� Design a <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong> <strong>Memory</strong><br />
� Challenges and Opportunities in <strong>3D</strong> CT<br />
<strong>NAND</strong> <strong>Flash</strong> <strong>Memory</strong><br />
� Summary<br />
2
Source<br />
Floating Gate (FG) <strong>Flash</strong> <strong>Memory</strong><br />
Control<br />
gate<br />
ONO<br />
Floating<br />
gate<br />
Oxide<br />
Drain<br />
Single cell structure<br />
~10F 2<br />
~4F 2<br />
� 1967 FG Transistor invented by D. Kahng and S. M. Sze (Bell Labs)<br />
� 1984 NOR <strong>Flash</strong> invented by Fujio Masuoka (Toshiba)<br />
� 1987 <strong>NAND</strong> <strong>Flash</strong> invented also by Fujio Masuoka (Toshiba)<br />
3
<strong>Flash</strong> <strong>Memory</strong> Applications<br />
<strong>NAND</strong><br />
(High Density for Data Storage)<br />
<strong>Flash</strong> <strong>Memory</strong><br />
NOR<br />
(Fast for Code Access)<br />
4
Scaling of FG <strong>NAND</strong> <strong>Memory</strong> (2D)<br />
0.25um<br />
K. Shimizu, et al.,<br />
(Toshiba) IEDM 1997<br />
1/100 of area in 13 years<br />
(~ 2 6.5 increase, or one<br />
node per 2 years)<br />
90nm<br />
D.C. Kim, et al., (Samsung)<br />
IEDM 2002<br />
25nm<br />
K. Prall, et al., (Micron)<br />
IEDM 2010 5
Design Rule (nm)<br />
100<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
Recent Scaling is Even Faster<br />
07<br />
Q1 Q2 Q3 Q4<br />
(at 1.5 Year/Gen)<br />
08<br />
Q1 Q2 Q3 Q4<br />
09<br />
Q1 Q2 Q3 Q4<br />
YEAR<br />
10<br />
Q1 Q2 Q3 Q4<br />
IMFT<br />
Samsung<br />
Toshiba<br />
Hynix<br />
11<br />
Q1 Q2 Q3 Q4<br />
6
2D Scaling Fulfills Demands and<br />
Creates New Applications<br />
Kinam Kim (Samsung), IMW 2010<br />
7
However, 2D Scaling is Running Out<br />
ONO and<br />
Tunnel Oxide<br />
can’t be scaled.<br />
For the same Vt window,<br />
∆Q = C * ∆Vt,<br />
Source<br />
of Electrons<br />
Control<br />
gate<br />
ONO<br />
Floating<br />
gate<br />
Tunnel<br />
Oxide<br />
Drain<br />
Single cell structure<br />
the electron number<br />
decreases as <strong>NAND</strong> cells are<br />
scaled down.<br />
Ne: Electron Number<br />
1000<br />
100<br />
10<br />
Electron number of FG<br />
GCR=0.7, Tono=15 nm, Tox=9nm<br />
GCR=0.65, Tono=13 nm, Tox=8nm<br />
10 100<br />
Technology Node: F (nm)<br />
Number of electrons in FG<br />
device (~ 20 for 10nm device)<br />
8
Impact of the Small Number of Electrons<br />
Number of electrons per logic level<br />
Node 45nm 32nm 22nm 16nm 11nm 8nm<br />
SLC 400 200 100 50 25 13<br />
(2 levels)<br />
MLC 140 70 35 18 10 5<br />
(4 levels)<br />
TLC 60 30 15 8 4 2<br />
(8 levels)<br />
QLC 30 15 8 4 2 1<br />
(16 levels)<br />
OLC 2 1 0.5 0.2 0.1 0.05<br />
(256 levels)<br />
Statistical fluctuation ~ √N / N. N = 10 ���� 30%.<br />
9
Solution is the <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong><br />
2-layer TANOS <strong>NAND</strong><br />
(Epitaxial Si growth)<br />
Samsung: IEDM 2006<br />
Stack up 2D devices<br />
C.Y. Lu (Macronix), Semicon Taiwan 2010<br />
2-layer BE-SONOS<br />
<strong>NAND</strong> (TFT device)<br />
Macronix: IEDM 2006<br />
Punch through<br />
multiple layers<br />
Bit-cost scalable<br />
(BiCS) TFT SONOS<br />
Toshiba: VLSI 2007<br />
10
Difference between <strong>3D</strong> Stacked <strong>NAND</strong><br />
and BiCS<br />
H. Tanaka, et al., (TOSHIBA),<br />
VLSI 2007<br />
� Both types maintain the electron number at a reasonable level.<br />
� <strong>3D</strong> Stacked <strong>NAND</strong> can’t further reduce cost when layer number >=4.<br />
� BiCS uses only one critical contact drill hole for many layers so the<br />
bit cost is scalable, even when more than 16 layers are used.<br />
11<br />
� Later <strong>3D</strong> <strong>NAND</strong> technologies have followed the BiCS concept.
Outline<br />
� Why Does <strong>NAND</strong> Go to <strong>3D</strong>?<br />
� Design a <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong> <strong>Memory</strong><br />
� Challenges and Opportunities in <strong>3D</strong> CT<br />
<strong>NAND</strong> <strong>Flash</strong> <strong>Memory</strong><br />
� Summary<br />
12
To Build <strong>3D</strong> <strong>NAND</strong>, Start from 2D<br />
� Conventional structure<br />
� <strong>Charge</strong>s stored in FG<br />
� <strong>Charge</strong>s in/out through<br />
the tunnel oxide.<br />
� SONOS CT structure<br />
� <strong>Charge</strong>s stored in nitride<br />
� <strong>Charge</strong>s in/out through<br />
the tunnel dielectric (ONO here).<br />
13
How <strong>NAND</strong> <strong>Flash</strong> Works?<br />
Asymmetric E-fields and Jg On/Off Ratio<br />
CG<br />
• P/E • High On/Off Ratio<br />
Program Erase<br />
E blocking<br />
IPD/<br />
Blocking Oxide<br />
E tunnel<br />
e- e- Tunnel<br />
Oxide<br />
<strong>Charge</strong><br />
Storage<br />
Substrate<br />
CG<br />
E blocking<br />
e- e- IPD/<br />
Blocking Oxide<br />
<strong>Charge</strong><br />
Storage<br />
E tunnel<br />
Tunnel<br />
Oxide<br />
h + h +<br />
� FG: GCR design<br />
� CT: high WF CG<br />
high-K blocking<br />
ONO tunnel dielectric<br />
Substrate<br />
Jg (log scale)<br />
Good<br />
Retention<br />
Fast P/E<br />
E-field<br />
14
Glance over Various 2D CT Devices<br />
Best reported reliability,<br />
no new process<br />
H. T. Lue et al., (Macronix), TDMR 2010<br />
Theoretically<br />
the highest<br />
performance<br />
15
Retention of 2D BE-SONOS <strong>NAND</strong><br />
H.T. Lue, et al.,<br />
(Macronix),<br />
IEDM 2005<br />
75nm BE-SONOS (Non-cut-ONO), P/E=1K<br />
V T (V)<br />
� Retention is excellent, and there is no single tail bit.<br />
� The best reported CT reliability so far.<br />
� BE-SONOS fundamentally solves traditional CT erase-retention<br />
dilemma.<br />
Bit Counts<br />
10 5<br />
10 4<br />
10 3<br />
10 2<br />
10 1<br />
10 0<br />
Disturbed EV<br />
150C Baking<br />
Before bake<br />
10min<br />
100min<br />
1100min<br />
5420min<br />
7230min<br />
10080min<br />
C. C. Hsieh, et al., (Macronix), IEDM 2010<br />
PV<br />
16
CT is Easier than FG for <strong>3D</strong><br />
SungJin Whang, et al., (Hynix),<br />
IEDM 2010<br />
� <strong>3D</strong> CT devices are simpler in topology.<br />
� <strong>3D</strong> CT devices are smaller than <strong>3D</strong> FG devices.<br />
� CT is more process-friendly.<br />
C.H. Hung, et al., (Macronix),<br />
VLSI 2011<br />
17
SONOS/TANOS<br />
FG<br />
Various <strong>3D</strong> <strong>NAND</strong> Architectures<br />
~2006 2007 2008 2009 2010 2011<br />
Stacked <strong>NAND</strong><br />
IEDM 2006<br />
Multi TFT<br />
IEDM 2006<br />
Univ. of Tokyo<br />
S-SGT<br />
IEDM 2001<br />
BiCS<br />
VLSI Symp<br />
Stacking Devices:<br />
High Process Cost<br />
P-BiCS<br />
VLSI Symp<br />
TCAT<br />
VLSI Symp<br />
VSAT<br />
VLSI Symp<br />
VG-<strong>NAND</strong><br />
VLSI Symp<br />
VG TFT<br />
VLSI Symp<br />
DC -SF<br />
IEDM<br />
Hybrid <strong>3D</strong><br />
IMW<br />
PNVG TFT<br />
VLSI Symp<br />
BiCS Concept: Low Process Cost<br />
18
In 2010, the Last of Several Crucial<br />
Elements Fell into Place for <strong>3D</strong> <strong>NAND</strong><br />
2005, BE-SONOS, (Macronix)<br />
2007, BiCS (Toshiba)<br />
2009, Vertical Gate (VG) <strong>NAND</strong> (Samsung)<br />
2010, <strong>3D</strong> Decoding (Macronix)<br />
There are occasionally short windows in time when incredibly<br />
important things get invented that shape the lives of humans<br />
– Steve Wozniak<br />
19
Macronix’s BE-SONOS <strong>3D</strong> <strong>NAND</strong><br />
� 75nm half-pitch, 8-layer device is fabricated.<br />
� Equivalent cell size = 0.001406 um 2 (MLC).<br />
� Each device is a double-gate TFT BE-SONOS device.<br />
H. T. Lue et al., (Macronix), VLSI 2010<br />
20
<strong>3D</strong> Decoding Method A —<br />
by Using Island Gate Devices<br />
H. T. Lue, et al., (Macronix), VLSI 2010<br />
� The method uses self-boosting scheme.<br />
� Conventional WL, BL are grouped into “planes”.<br />
� One additional SSL’s device also grouped into “planes”.<br />
� Three planes select a memory cell.<br />
21
<strong>3D</strong> Decoding Method B —<br />
by Using P-N Polysilicon Diode<br />
� 1 st phase, decodes a <strong>NAND</strong> vertical plane, by conventional selfboosting.<br />
� 2 nd phase, decodes a layer in the selected plane by source-side<br />
biasing.<br />
C.H. Hung et al., (Macronix), VLSI 2011<br />
22
Comparison among the Architectures<br />
[P-BiCS] R. Katsumata, et al, VLSI Symposia, pp. 136-137, 2009. [TCAT] J. Jang, et al, VLSI Symposia, pp. 192-193, 2009. [VSAT]<br />
J. Kim, et al, VLSI Symposia, pp. 186-187, 2009. [VG] W. Kim, et al, VLSI Symposia, pp. 188-189, 2009.<br />
23
Outline<br />
� Why Does <strong>NAND</strong> Go to <strong>3D</strong>?<br />
� Design a <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong> <strong>Memory</strong><br />
� Challenges and Opportunities in <strong>3D</strong> CT<br />
<strong>NAND</strong> <strong>Flash</strong> <strong>Memory</strong><br />
� Summary<br />
24
Process Integration for <strong>3D</strong> CT <strong>NAND</strong><br />
<strong>Flash</strong> <strong>Memory</strong><br />
� <strong>3D</strong> memory in FEOL or BEOL?<br />
� CMOS under or beside the memory array?<br />
� How to handle PL layers left on periphery area<br />
� Planarization between <strong>3D</strong> memory and 2D CMOS<br />
� Thermal budget management<br />
Takashi Maeda, et al., (Toshiba), VLSI 2009<br />
25
HK-MG for Better Performance<br />
� HK can reduce the E-field and suppress the gate injection.<br />
� MG can reduce WL resistivity for faster R/W.<br />
� SEMATECH has been engaging HK-MG for years. The<br />
experience should be very useful to <strong>3D</strong> CT <strong>NAND</strong><br />
community.<br />
Jaehoon Jang, et al., (Samsung), VLSI 2009<br />
26
Contact Holes for Layers<br />
H. Tanaka, et al., (Toshiba), VLSI 2007<br />
Jaehoon Jang, et al., (Samsung), VLSI 2009<br />
� Contact holes for layers are very<br />
area consuming.<br />
� Which approach is the most<br />
compact and manufacturable?<br />
Jiyoung Jim, et al., (UCLA), VLSI 2008<br />
27
Patterning and Etching<br />
� At 5xnm node, <strong>3D</strong> memory<br />
should be more than 32<br />
layers, in order to compete<br />
with 1Z nm MLC <strong>NAND</strong>.<br />
� For 30nm layer pitch, 32<br />
layers gives a stack height<br />
of 960nm.<br />
� The hole etching is<br />
challenging not only due<br />
to the high A/R but also<br />
due to different materials.<br />
Jungdal Choi, et al., (Samsung), VLSI 2011<br />
28
Scaling or Stacking or MLC<br />
� In <strong>3D</strong> VG <strong>NAND</strong>, there<br />
are 3 ways to shrink<br />
equivalent cell size.<br />
� Pitch scaling<br />
� BL gap fill-in<br />
� WL bridging<br />
� Layer stacking<br />
� Deep etching and<br />
profile control<br />
� Multi-level cell<br />
� Device variation<br />
� Which is the right way in<br />
terms of business?<br />
Relative Bit Cost<br />
Ref. (25nm MLC FG <strong>NAND</strong>)<br />
1<br />
Log scale<br />
F=66nm, 6F 2<br />
F=50nm, 6F 2<br />
F=35nm, 4F 2<br />
F=25nm, 4F 2<br />
F=25nm, 6F 2<br />
VG possible<br />
0 5 10 15 20 25 30<br />
Number of Layer for <strong>3D</strong> stacks<br />
29
Polysilicon TFT Channel Engineering<br />
M. Mizukami, et al., (Toshiba), SSDM 2009<br />
� The Worst-On-Current (WOC) of<br />
the <strong>NAND</strong> string is strongly<br />
affected by the electron mobility<br />
in polysilicon. It should be<br />
carefully engineered.<br />
� Polysilicon uniformity on the<br />
same layer and layer-to-layer<br />
uniformity are both challenging.<br />
Y. Fukuzumi, et al., (Toshiba), VLSI 2007<br />
30
In 2D-to-<strong>3D</strong> Paradigm Shift,<br />
Challenges = Opportunities<br />
� By 2013, <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong> is going<br />
into commercialization. This will<br />
be the biggest paradigm shift in<br />
NVM business.<br />
Jungdal Choi, et al., (Samsung), VLSI 2011<br />
� To make <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong><br />
happen, collaboration should be<br />
considered.<br />
31
Summary<br />
� 2D FG <strong>NAND</strong> is running out of electrons. <strong>3D</strong> is a<br />
must to meet demands.<br />
� For <strong>3D</strong> <strong>NAND</strong> <strong>Flash</strong>, CT type is more processfriendly,<br />
and VG is the most scalable architecture.<br />
� Single deep etching (for realizing the BiCS<br />
concept) and polysilicon TFT device uniformity are<br />
the most challenging topics.<br />
� Macronix and other <strong>NAND</strong> giants are dedicated in<br />
this field for years. To accelerate the progress,<br />
collaboration is a good way, and should be<br />
considered.<br />
32