3D Charge Trapping NAND Flash Memory - Sematech

3D Charge Trapping (CT) NAND Flash
Yen-Hao Shih
Macronix International Co., Ltd.
Hsinchu, Hsinchu,
Taiwan
Email: yhshih@mxic.com.tw
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Outline
� Why Does NAND Go to 3D?
� Design a 3D NAND Flash Memory
� Challenges and Opportunities in 3D CT
NAND Flash Memory
� Summary
2

Source
Floating Gate (FG) Flash Memory
Control
gate
ONO
Floating
gate
Oxide
Drain
Single cell structure
~10F 2
~4F 2
� 1967 FG Transistor invented by D. Kahng and S. M. Sze (Bell Labs)
� 1984 NOR Flash invented by Fujio Masuoka (Toshiba)
� 1987 NAND Flash invented also by Fujio Masuoka (Toshiba)
3

Flash Memory Applications
NAND
(High Density for Data Storage)
Flash Memory
NOR
(Fast for Code Access)
4

Scaling of FG NAND Memory (2D)
0.25um
K. Shimizu, et al.,
(Toshiba) IEDM 1997
1/100 of area in 13 years
(~ 2 6.5 increase, or one
node per 2 years)
90nm
D.C. Kim, et al., (Samsung)
IEDM 2002
25nm
K. Prall, et al., (Micron)
IEDM 2010 5

Design Rule (nm)
100
60
50
40
30
20
10
Recent Scaling is Even Faster
07
Q1 Q2 Q3 Q4
(at 1.5 Year/Gen)
08
Q1 Q2 Q3 Q4
09
Q1 Q2 Q3 Q4
YEAR
10
Q1 Q2 Q3 Q4
IMFT
Samsung
Toshiba
Hynix
11
Q1 Q2 Q3 Q4
6

2D Scaling Fulfills Demands and
Creates New Applications
Kinam Kim (Samsung), IMW 2010
7

However, 2D Scaling is Running Out
ONO and
Tunnel Oxide
can’t be scaled.
For the same Vt window,
∆Q = C * ∆Vt,
Source
of Electrons
Control
gate
ONO
Floating
gate
Tunnel
Oxide
Drain
Single cell structure
the electron number
decreases as NAND cells are
scaled down.
Ne: Electron Number
1000
100
10
Electron number of FG
GCR=0.7, Tono=15 nm, Tox=9nm
GCR=0.65, Tono=13 nm, Tox=8nm
10 100
Technology Node: F (nm)
Number of electrons in FG
device (~ 20 for 10nm device)
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Impact of the Small Number of Electrons
Number of electrons per logic level
Node 45nm 32nm 22nm 16nm 11nm 8nm
SLC 400 200 100 50 25 13
(2 levels)
MLC 140 70 35 18 10 5
(4 levels)
TLC 60 30 15 8 4 2
(8 levels)
QLC 30 15 8 4 2 1
(16 levels)
OLC 2 1 0.5 0.2 0.1 0.05
(256 levels)
Statistical fluctuation ~ √N / N. N = 10 ���� 30%.
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Solution is the 3D NAND Flash
2-layer TANOS NAND
(Epitaxial Si growth)
Samsung: IEDM 2006
Stack up 2D devices
C.Y. Lu (Macronix), Semicon Taiwan 2010
2-layer BE-SONOS
NAND (TFT device)
Macronix: IEDM 2006
Punch through
multiple layers
Bit-cost scalable
(BiCS) TFT SONOS
Toshiba: VLSI 2007
10

Difference between 3D Stacked NAND
and BiCS
H. Tanaka, et al., (TOSHIBA),
VLSI 2007
� Both types maintain the electron number at a reasonable level.
� 3D Stacked NAND can’t further reduce cost when layer number >=4.
� BiCS uses only one critical contact drill hole for many layers so the
bit cost is scalable, even when more than 16 layers are used.
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� Later 3D NAND technologies have followed the BiCS concept.

Outline
� Why Does NAND Go to 3D?
� Design a 3D NAND Flash Memory
� Challenges and Opportunities in 3D CT
NAND Flash Memory
� Summary
12

To Build 3D NAND, Start from 2D
� Conventional structure
� Charges stored in FG
� Charges in/out through
the tunnel oxide.
� SONOS CT structure
� Charges stored in nitride
� Charges in/out through
the tunnel dielectric (ONO here).
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How NAND Flash Works?
Asymmetric E-fields and Jg On/Off Ratio
CG
• P/E • High On/Off Ratio
Program Erase
E blocking
IPD/
Blocking Oxide
E tunnel
e- e- Tunnel
Oxide
Charge
Storage
Substrate
CG
E blocking
e- e- IPD/
Blocking Oxide
Charge
Storage
E tunnel
Tunnel
Oxide
h + h +
� FG: GCR design
� CT: high WF CG
high-K blocking
ONO tunnel dielectric
Substrate
Jg (log scale)
Good
Retention
Fast P/E
E-field
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Glance over Various 2D CT Devices
Best reported reliability,
no new process
H. T. Lue et al., (Macronix), TDMR 2010
Theoretically
the highest
performance
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Retention of 2D BE-SONOS NAND
H.T. Lue, et al.,
(Macronix),
IEDM 2005
75nm BE-SONOS (Non-cut-ONO), P/E=1K
V T (V)
� Retention is excellent, and there is no single tail bit.
� The best reported CT reliability so far.
� BE-SONOS fundamentally solves traditional CT erase-retention
dilemma.
Bit Counts
10 5
10 4
10 3
10 2
10 1
10 0
Disturbed EV
150C Baking
Before bake
10min
100min
1100min
5420min
7230min
10080min
C. C. Hsieh, et al., (Macronix), IEDM 2010
PV
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CT is Easier than FG for 3D
SungJin Whang, et al., (Hynix),
IEDM 2010
� 3D CT devices are simpler in topology.
� 3D CT devices are smaller than 3D FG devices.
� CT is more process-friendly.
C.H. Hung, et al., (Macronix),
VLSI 2011
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SONOS/TANOS
FG
Various 3D NAND Architectures
~2006 2007 2008 2009 2010 2011
Stacked NAND
IEDM 2006
Multi TFT
IEDM 2006
Univ. of Tokyo
S-SGT
IEDM 2001
BiCS
VLSI Symp
Stacking Devices:
High Process Cost
P-BiCS
VLSI Symp
TCAT
VLSI Symp
VSAT
VLSI Symp
VG-NAND
VLSI Symp
VG TFT
VLSI Symp
DC -SF
IEDM
Hybrid 3D
IMW
PNVG TFT
VLSI Symp
BiCS Concept: Low Process Cost
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In 2010, the Last of Several Crucial
Elements Fell into Place for 3D NAND
2005, BE-SONOS, (Macronix)
2007, BiCS (Toshiba)
2009, Vertical Gate (VG) NAND (Samsung)
2010, 3D Decoding (Macronix)
There are occasionally short windows in time when incredibly
important things get invented that shape the lives of humans
– Steve Wozniak
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Macronix’s BE-SONOS 3D NAND
� 75nm half-pitch, 8-layer device is fabricated.
� Equivalent cell size = 0.001406 um 2 (MLC).
� Each device is a double-gate TFT BE-SONOS device.
H. T. Lue et al., (Macronix), VLSI 2010
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3D Decoding Method A —
by Using Island Gate Devices
H. T. Lue, et al., (Macronix), VLSI 2010
� The method uses self-boosting scheme.
� Conventional WL, BL are grouped into “planes”.
� One additional SSL’s device also grouped into “planes”.
� Three planes select a memory cell.
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3D Decoding Method B —
by Using P-N Polysilicon Diode
� 1 st phase, decodes a NAND vertical plane, by conventional selfboosting.
� 2 nd phase, decodes a layer in the selected plane by source-side
biasing.
C.H. Hung et al., (Macronix), VLSI 2011
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Comparison among the Architectures
[P-BiCS] R. Katsumata, et al, VLSI Symposia, pp. 136-137, 2009. [TCAT] J. Jang, et al, VLSI Symposia, pp. 192-193, 2009. [VSAT]
J. Kim, et al, VLSI Symposia, pp. 186-187, 2009. [VG] W. Kim, et al, VLSI Symposia, pp. 188-189, 2009.
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Outline
� Why Does NAND Go to 3D?
� Design a 3D NAND Flash Memory
� Challenges and Opportunities in 3D CT
NAND Flash Memory
� Summary
24

Process Integration for 3D CT NAND
Flash Memory
� 3D memory in FEOL or BEOL?
� CMOS under or beside the memory array?
� How to handle PL layers left on periphery area
� Planarization between 3D memory and 2D CMOS
� Thermal budget management
Takashi Maeda, et al., (Toshiba), VLSI 2009
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HK-MG for Better Performance
� HK can reduce the E-field and suppress the gate injection.
� MG can reduce WL resistivity for faster R/W.
� SEMATECH has been engaging HK-MG for years. The
experience should be very useful to 3D CT NAND
community.
Jaehoon Jang, et al., (Samsung), VLSI 2009
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Contact Holes for Layers
H. Tanaka, et al., (Toshiba), VLSI 2007
Jaehoon Jang, et al., (Samsung), VLSI 2009
� Contact holes for layers are very
area consuming.
� Which approach is the most
compact and manufacturable?
Jiyoung Jim, et al., (UCLA), VLSI 2008
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Patterning and Etching
� At 5xnm node, 3D memory
should be more than 32
layers, in order to compete
with 1Z nm MLC NAND.
� For 30nm layer pitch, 32
layers gives a stack height
of 960nm.
� The hole etching is
challenging not only due
to the high A/R but also
due to different materials.
Jungdal Choi, et al., (Samsung), VLSI 2011
28

Scaling or Stacking or MLC
� In 3D VG NAND, there
are 3 ways to shrink
equivalent cell size.
� Pitch scaling
� BL gap fill-in
� WL bridging
� Layer stacking
� Deep etching and
profile control
� Multi-level cell
� Device variation
� Which is the right way in
terms of business?
Relative Bit Cost
Ref. (25nm MLC FG NAND)
1
Log scale
F=66nm, 6F 2
F=50nm, 6F 2
F=35nm, 4F 2
F=25nm, 4F 2
F=25nm, 6F 2
VG possible
0 5 10 15 20 25 30
Number of Layer for 3D stacks
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Polysilicon TFT Channel Engineering
M. Mizukami, et al., (Toshiba), SSDM 2009
� The Worst-On-Current (WOC) of
the NAND string is strongly
affected by the electron mobility
in polysilicon. It should be
carefully engineered.
� Polysilicon uniformity on the
same layer and layer-to-layer
uniformity are both challenging.
Y. Fukuzumi, et al., (Toshiba), VLSI 2007
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In 2D-to-3D Paradigm Shift,
Challenges = Opportunities
� By 2013, 3D NAND Flash is going
into commercialization. This will
be the biggest paradigm shift in
NVM business.
Jungdal Choi, et al., (Samsung), VLSI 2011
� To make 3D NAND Flash
happen, collaboration should be
considered.
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Summary
� 2D FG NAND is running out of electrons. 3D is a
must to meet demands.
� For 3D NAND Flash, CT type is more processfriendly,
and VG is the most scalable architecture.
� Single deep etching (for realizing the BiCS
concept) and polysilicon TFT device uniformity are
the most challenging topics.
� Macronix and other NAND giants are dedicated in
this field for years. To accelerate the progress,
collaboration is a good way, and should be
considered.
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