uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
96<br />
CHAPTER 9 WATCHDOG TIMER<br />
9.4.2 Operation as interval timer<br />
When bits 4 and 3 (WDTM4, WDTM3) of watchdog timer mode register (WDTM) are set to 1, the watchdog timer<br />
also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value<br />
set in advance.<br />
Select a count clock (or interval time) by setting bits 1 and 2 (WDCS1 and WDCS2) of watchdog timer clock select<br />
register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set<br />
to 1.<br />
In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be<br />
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.<br />
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to<br />
1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.<br />
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected),<br />
the interval timer mode is not set, unless the RESET signal is input.<br />
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than<br />
the set time.<br />
Table 9-5. Interval Time of Interval Timer<br />
WDCS2 WDCS1 At fX = 5.0 MHz Operation<br />
0 0 410 µs<br />
0 1 1.64 ms<br />
1 0 6.55 ms<br />
1 1 26.2 ms<br />
fX: Main system clock oscillation frequency<br />
Preliminary User’s Manual U14938EJ1V0UM