uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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CHAPTER 9 WATCHDOG TIMER
9.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of watchdog timer mode register (WDTM) are set to 1, the watchdog timer
also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value
set in advance.
Select a count clock (or interval time) by setting bits 1 and 2 (WDCS1 and WDCS2) of watchdog timer clock select
register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set
to 1.
In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to
1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected),
the interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than
the set time.
Table 9-5. Interval Time of Interval Timer
WDCS2 WDCS1 At fX = 5.0 MHz Operation
0 0 410 µs
0 1 1.64 ms
1 0 6.55 ms
1 1 26.2 ms
fX: Main system clock oscillation frequency
Preliminary User’s Manual U14938EJ1V0UM