uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

5.3 Register Controlling Clock Generator
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CHAPTER 5 CLOCK GENERATOR
The clock generator is controlled by the following registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC sets the CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 02H.
Figure 5-2. Processor Clock Control Register Format
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PCC
MCC 0 0 0 0 0 PCC1 0
MCC
0
1
CSS0
0
0
1
1
Operation enabled
Operation stopped
PCC1
0
1
0
1
fX (0.2 µ s)
fX/22 (0.8 µ
s)
fXT/2 (61 µ s)
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC and the CSS0 flag in the subclock control register (CSS) (refer to 5.3 (3) subclock
control register (CSS)).
Cautions 1. Bit 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
4. Minimum instruction execution time: 2fCPU
• fCPU = 0.2 µs: 0.4 µs
• fCPU = 0.8 µs: 1.6 µs
• fCPU = 61 µs: 122 µs
Control of main system clock oscillator operation
Preliminary User’s Manual U14938EJ1V0UM
FFFBH 02H R/W
CPU clock (fCPU) selection Note