uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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3.3.2 Immediate addressing 46 CHAPTER 3 CPU ARCHITECTURE [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “CALL !addr16 and BR !addr16” instructions are executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. [Illustration] In case of CALL !addr16, BR !addr16 instruction PC 7 0 CALL or BR Low Addr. High Addr. 15 8 7 0 Preliminary User’s Manual U14938EJ1V0UM
3.3.3 Table indirect addressing CHAPTER 3 CPU ARCHITECTURE [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces. [Illustration] 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the “BR AX” instruction is executed. [Illustration] Instruction code Effective address + 1 PC 15 8 7 6 5 1 0 Effective address 0 0 0 0 0 0 0 0 0 1 rp PC 7 6 5 1 0 1 1 ta4–0 7 Memory (Table) 0 Low Addr. High Addr. 1 15 8 7 0 7 0 7 0 A X 15 8 7 0 Preliminary User’s Manual U14938EJ1V0UM 47 0
Page 1 and 2: To our customers, Old Company Name
Page 3 and 4: Preliminary User’s Manual µPD789
Page 5 and 6: 1 NOTES FOR CMOS DEVICES PRECAUTION
Page 7 and 8: Regional Information Some informati
Page 9 and 10: Documents Related to Devices Docume
Page 11 and 12: CONTENTS CHAPTER 1 GENERAL ........
Page 13 and 14: CHAPTER 8 WATCH TIMER .............
Page 15 and 16: LIST OF FIGURES (1/3) Figure No. Ti
Page 17 and 18: LIST OF FIGURES (3/3) Figure No. Ti
Page 19 and 20: LIST OF TABLES (2/2) Table No. Titl
Page 21 and 22: 1.4 Pin Configuration (Top View)
Page 23 and 24: CHAPTER 1 GENERAL The major functio
Page 25 and 26: An outline of the timer is shown be
Page 27 and 28: (2) Non-port pins CHAPTER 2 PIN FUN
Page 29 and 30: CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
Page 31 and 32: CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
Page 33 and 34: 3.1 Memory Space CHAPTER 3 CPU ARCH
Page 35 and 36: Data memory space Program memory sp
Page 37 and 38: CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
Page 39 and 40: FFFFH FF20H FF1FH FF00H FEFFH FE20H
Page 41 and 42: 3.2 Processor Registers CHAPTER 3 C
Page 43 and 44: CHAPTER 3 CPU ARCHITECTURE (3) Stac
Page 45 and 46: CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
Page 47: 3.3 Instruction Address Addressing
Page 51 and 52: 3.4.2 Short direct addressing CHAPT
Page 53 and 54: 3.4.4 Register addressing CHAPTER 3
Page 55 and 56: 3.4.6 Based addressing CHAPTER 3 CP
Page 57 and 58: CHAPTER 4 PORT FUNCTIONS Table 4-1.
Page 59 and 60: CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
Page 61 and 62: Internal bus WRPUB2 RD WRPORT WRPM
Page 63 and 64: CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
Page 65 and 66: 4.3 Port Function Control Registers
Page 67 and 68: 4.4 Operation of Port Functions CHA
Page 69 and 70: XT1 XT2 X1 X2 Internal bus FRC SCC
Page 71 and 72: CHAPTER 5 CLOCK GENERATOR (2) Subos
Page 73 and 74: CHAPTER 5 CLOCK GENERATOR Figure 5-
Page 75 and 76: 5.5 Clock Generator Operation CHAPT
Page 77 and 78: CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
Page 79 and 80: CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 81 and 82: CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 83 and 84: 7.2 8-Bit Timer Configuration The 8
Page 85 and 86: 7.3 Registers Controlling 8-Bit Tim
Page 87 and 88: 7.4 8-Bit Timer Operation CHAPTER 7
Page 89 and 90: 8.1 Watch Timer Functions The watch
Page 91 and 92: WTM CHAPTER 8 WATCH TIMER Figure 8-
Page 93 and 94: CHAPTER 9 WATCHDOG TIMER The watchd
Page 95 and 96: 9.3 Registers Controlling Watchdog
Page 97 and 98: 9.4 Watchdog Timer Operation CHAPTE
Page 99 and 100:
10.1 Serial Interface 10 Functions
Page 101 and 102:
10.3 Register Controlling Serial In
Page 103 and 104:
10.4 Serial Interface 10 Operation
Page 105 and 106:
CHAPTER 10 SERIAL INTERFACE 10 (2)
Page 107 and 108:
11.2 VFD Controller/Driver Configur
Page 109 and 110:
(2) Display mode register 1 (DSPM1)
Page 111 and 112:
CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 113 and 114:
CHAPTER 11 VFD CONTROLLER/DRIVER (2
Page 115 and 116:
CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 117 and 118:
T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
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CHAPTER 11 VFD CONTROLLER/DRIVER By
Page 121 and 122:
12.1 Interrupt Function Types CHAPT
Page 123 and 124:
(A) Internal non-maskable interrupt
Page 125 and 126:
12.3 Interrupt Function Control Reg
Page 127 and 128:
CHAPTER 12 INTERRUPT FUNCTIONS (2)
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CHAPTER 12 INTERRUPT FUNCTIONS (4)
Page 131 and 132:
CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 133 and 134:
CHAPTER 12 INTERRUPT FUNCTIONS Figu
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INTxx CHAPTER 12 INTERRUPT FUNCTION
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13.1 Standby Function and Configura
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13.2 Operation of Standby Function
Page 141 and 142:
CHAPTER 13 STANDBY FUNCTION (c) Rel
Page 143 and 144:
CHAPTER 13 STANDBY FUNCTION (2) Rel
Page 145 and 146:
CHAPTER 14 RESET FUNCTION The follo
Page 147 and 148:
CHAPTER 14 RESET FUNCTION Table 14-
Page 149 and 150:
15.1 Flash Memory Programming VPP R
Page 151 and 152:
CHAPTER 15 µPD78F9872 15.1.4 Examp
Page 153 and 154:
CHAPTER 17 INSTRUCTION SET This cha
Page 155 and 156:
17.2 Operation List CHAPTER 17 INST
Page 157 and 158:
CHAPTER 17 INSTRUCTION SET Mnemonic
Page 159 and 160:
CHAPTER 17 INSTRUCTION SET Mnemonic
Page 161 and 162:
CHAPTER 17 INSTRUCTION SET (2) 16-b
Page 163 and 164:
APPENDIX A DEVELOPMENT TOOLS The fo
Page 165 and 166:
A.1 Language Processing Software AP
Page 167 and 168:
A.3.2 Software ID78K0S-NS Integrate
Page 169 and 170:
C.1 Register Name Index (Alphabetic
Page 171 and 172:
C.2 Register Symbol Index (Alphabet
Page 173:
Facsimile Message From: Name Compan
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