uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
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40<br />
CHAPTER 3 CPU ARCHITECTURE<br />
(a) Interrupt enable flag (IE)<br />
This flag controls interrupt request acknowledge operations of CPU.<br />
When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable<br />
interrupt are disabled.<br />
When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is<br />
controlled with an interrupt mask flag for various interrupt sources.<br />
This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI<br />
instruction execution.<br />
(b) Zero flag (Z)<br />
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.<br />
(c) Auxiliary carry flag (AC)<br />
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset (0) in<br />
all other cases.<br />
(d) Carry flag (CY)<br />
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out<br />
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation<br />
instruction execution.<br />
Preliminary User’s Manual U14938EJ1V0UM
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