uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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1.6 Block Diagram 22 TI/P25 SO10/P21 SI10/P22 SCK10/P20 INTP0/P23 INTP1/P24 8-bit remote control timer 50 8-bit timer 80 8-bit timer 81 Watch timer Watchdog timer Serial interface10 Interrupt control CHAPTER 1 GENERAL 78K/0S CPU core RAM 512 bytes ROM VDD0 VSS0 IC (VPP) Remarks 1. The internal ROM capacity varies depending on the product. 2. The parenthesized values apply to µPD78F9872. Preliminary User’s Manual U14938EJ1V0UM Port0 Port1 Port2 Port8 Port9 VFD controller/ driver System control P00 to P07 P10 to P12 P20 to P25 P80 to P87 P90 to P97 FIP0 to FIP8 FIP9/P97 to FIP16/P90 FIP17/P87 to FIP24/P80 VLOAD VDD1 RESET X1 X2 XT1 XT2
An outline of the timer is shown below. CHAPTER 1 GENERAL Preliminary User’s Manual U14938EJ1V0UM 8-Bit Watch Timer Watchdog Timer Timer Operation mode Interval timer – 1 channel 1 channelNote 1 1 channelNote 2 Function Pulse width 1 input – – – measurement Interrupt sources 3 2 1 1 Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has the watchdog timer and interval timer function. However, use the watchdog timer by selecting either the watchdog timer function or interval timer function. 1.7 Overview of Functions 8-Bit Remote Control Timer Item µPD789870 µPD789871 µPD78F9872 Internal memory ROM Mask ROM Flash memory High-speed RAM 512 bytes VFD display RAM 96 bytes 4 KB 8 KB 16 KB Minimum instruction execution time • 0.4 µs/1.6 µs (@ 5.0 MHz operation with main system clock) •122 µs (@ 32.768 kHz operation with subsystem clock) General-purpose registers 8 bits × 8 registers Instruction set • 16-bit operations • Bit manipulations (such as set, reset, and test) I/O ports Total: 33 • CMOS I/O: 17 • P-ch open-drain I/O: 8 • P-ch open-drain output: 8 VFD controller/driver Display output total: 25 Serial interfaces 3-wire serial I/O: 1 channel Timers • 8-bit remote control timer: 1 channel • 8-bit timer: 2 channels • Watch timer: 1 channel • Watchdog timer: 1 channel Vectored interrupt Maskable Internal: 8, external: 4 sources Non-maskable Internal: 1 Power supply voltage VDD = 2.7 to 5.5 V (in normal operation) Operating ambient temperature TA = –40 to +85°C VDD = 4.5 to 5.5 V (in VFD operation) Package 52-pin plastic LQFP (10 × 10) 23
Page 1 and 2: To our customers, Old Company Name
Page 3 and 4: Preliminary User’s Manual µPD789
Page 5 and 6: 1 NOTES FOR CMOS DEVICES PRECAUTION
Page 7 and 8: Regional Information Some informati
Page 9 and 10: Documents Related to Devices Docume
Page 11 and 12: CONTENTS CHAPTER 1 GENERAL ........
Page 13 and 14: CHAPTER 8 WATCH TIMER .............
Page 15 and 16: LIST OF FIGURES (1/3) Figure No. Ti
Page 17 and 18: LIST OF FIGURES (3/3) Figure No. Ti
Page 19 and 20: LIST OF TABLES (2/2) Table No. Titl
Page 21 and 22: 1.4 Pin Configuration (Top View)
Page 23: CHAPTER 1 GENERAL The major functio
Page 27 and 28: (2) Non-port pins CHAPTER 2 PIN FUN
Page 29 and 30: CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
Page 31 and 32: CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
Page 33 and 34: 3.1 Memory Space CHAPTER 3 CPU ARCH
Page 35 and 36: Data memory space Program memory sp
Page 37 and 38: CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
Page 39 and 40: FFFFH FF20H FF1FH FF00H FEFFH FE20H
Page 41 and 42: 3.2 Processor Registers CHAPTER 3 C
Page 43 and 44: CHAPTER 3 CPU ARCHITECTURE (3) Stac
Page 45 and 46: CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
Page 47 and 48: 3.3 Instruction Address Addressing
Page 49 and 50: 3.3.3 Table indirect addressing CHA
Page 51 and 52: 3.4.2 Short direct addressing CHAPT
Page 53 and 54: 3.4.4 Register addressing CHAPTER 3
Page 55 and 56: 3.4.6 Based addressing CHAPTER 3 CP
Page 57 and 58: CHAPTER 4 PORT FUNCTIONS Table 4-1.
Page 59 and 60: CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
Page 61 and 62: Internal bus WRPUB2 RD WRPORT WRPM
Page 63 and 64: CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
Page 65 and 66: 4.3 Port Function Control Registers
Page 67 and 68: 4.4 Operation of Port Functions CHA
Page 69 and 70: XT1 XT2 X1 X2 Internal bus FRC SCC
Page 71 and 72: CHAPTER 5 CLOCK GENERATOR (2) Subos
Page 73 and 74: CHAPTER 5 CLOCK GENERATOR Figure 5-
Page 75 and 76:
5.5 Clock Generator Operation CHAPT
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CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
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CHAPTER 6 8-BIT REMOTE CONTROL TIME
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CHAPTER 6 8-BIT REMOTE CONTROL TIME
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7.2 8-Bit Timer Configuration The 8
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7.3 Registers Controlling 8-Bit Tim
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7.4 8-Bit Timer Operation CHAPTER 7
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8.1 Watch Timer Functions The watch
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WTM CHAPTER 8 WATCH TIMER Figure 8-
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CHAPTER 9 WATCHDOG TIMER The watchd
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9.3 Registers Controlling Watchdog
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9.4 Watchdog Timer Operation CHAPTE
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10.1 Serial Interface 10 Functions
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10.3 Register Controlling Serial In
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10.4 Serial Interface 10 Operation
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CHAPTER 10 SERIAL INTERFACE 10 (2)
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11.2 VFD Controller/Driver Configur
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(2) Display mode register 1 (DSPM1)
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CHAPTER 11 VFD CONTROLLER/DRIVER 11
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CHAPTER 11 VFD CONTROLLER/DRIVER (2
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CHAPTER 11 VFD CONTROLLER/DRIVER 11
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T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
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CHAPTER 11 VFD CONTROLLER/DRIVER By
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12.1 Interrupt Function Types CHAPT
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(A) Internal non-maskable interrupt
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12.3 Interrupt Function Control Reg
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CHAPTER 12 INTERRUPT FUNCTIONS (2)
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CHAPTER 12 INTERRUPT FUNCTIONS (4)
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CHAPTER 12 INTERRUPT FUNCTIONS Figu
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CHAPTER 12 INTERRUPT FUNCTIONS Figu
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INTxx CHAPTER 12 INTERRUPT FUNCTION
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13.1 Standby Function and Configura
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13.2 Operation of Standby Function
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CHAPTER 13 STANDBY FUNCTION (c) Rel
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CHAPTER 13 STANDBY FUNCTION (2) Rel
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CHAPTER 14 RESET FUNCTION The follo
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CHAPTER 14 RESET FUNCTION Table 14-
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15.1 Flash Memory Programming VPP R
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CHAPTER 15 µPD78F9872 15.1.4 Examp
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CHAPTER 17 INSTRUCTION SET This cha
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17.2 Operation List CHAPTER 17 INST
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET (2) 16-b
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APPENDIX A DEVELOPMENT TOOLS The fo
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A.1 Language Processing Software AP
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A.3.2 Software ID78K0S-NS Integrate
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C.1 Register Name Index (Alphabetic
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C.2 Register Symbol Index (Alphabet
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Facsimile Message From: Name Compan
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uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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