uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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160 (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 1st Operand 2nd Operand CHAPTER 17 INSTRUCTION SET AX !addr16 [addr5] $addr16 Basic Instructions BR CALL CALLT BR BR BC BNC BZ BNZ Compound Instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U14938EJ1V0UM
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µPD789871 <strong>Subseries</strong>. Figure A-1 shows the development tool configuration. • Support of the PC98-NX Series Unless otherwise specified, the µPD789104A/114A/124A/134A <strong>Subseries</strong> supported by IBM PC/AT and compatibles can be used for the PC98-NX Series. When using the PC98-NX Series, refer to the descriptions of the IBM PC/AT and compatibles. • Windows Unless otherwise specified, “Windows” indicates the following OSs. Windows 3.1 Windows 95 Windows NT Ver. 4.0 Preliminary User’s Manual U14938EJ1V0UM 161
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To our customers, Old Company Name
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Preliminary User’s Manual µPD789
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1 NOTES FOR CMOS DEVICES PRECAUTION
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Regional Information Some informati
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Documents Related to Devices Docume
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CONTENTS CHAPTER 1 GENERAL ........
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CHAPTER 8 WATCH TIMER .............
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LIST OF FIGURES (1/3) Figure No. Ti
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LIST OF FIGURES (3/3) Figure No. Ti
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LIST OF TABLES (2/2) Table No. Titl
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1.4 Pin Configuration (Top View)
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CHAPTER 1 GENERAL The major functio
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An outline of the timer is shown be
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(2) Non-port pins CHAPTER 2 PIN FUN
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CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
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CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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Data memory space Program memory sp
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FE20H
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3.2 Processor Registers CHAPTER 3 C
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CHAPTER 3 CPU ARCHITECTURE (3) Stac
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CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
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3.3 Instruction Address Addressing
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3.3.3 Table indirect addressing CHA
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3.4.2 Short direct addressing CHAPT
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3.4.4 Register addressing CHAPTER 3
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3.4.6 Based addressing CHAPTER 3 CP
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CHAPTER 4 PORT FUNCTIONS Table 4-1.
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CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
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Internal bus WRPUB2 RD WRPORT WRPM
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CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
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4.3 Port Function Control Registers
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4.4 Operation of Port Functions CHA
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XT1 XT2 X1 X2 Internal bus FRC SCC
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CHAPTER 5 CLOCK GENERATOR (2) Subos
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CHAPTER 5 CLOCK GENERATOR Figure 5-
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5.5 Clock Generator Operation CHAPT
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CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
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CHAPTER 6 8-BIT REMOTE CONTROL TIME
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CHAPTER 6 8-BIT REMOTE CONTROL TIME
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7.2 8-Bit Timer Configuration The 8
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7.3 Registers Controlling 8-Bit Tim
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7.4 8-Bit Timer Operation CHAPTER 7
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8.1 Watch Timer Functions The watch
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WTM CHAPTER 8 WATCH TIMER Figure 8-
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CHAPTER 9 WATCHDOG TIMER The watchd
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9.3 Registers Controlling Watchdog
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9.4 Watchdog Timer Operation CHAPTE
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10.1 Serial Interface 10 Functions
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10.3 Register Controlling Serial In
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10.4 Serial Interface 10 Operation
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CHAPTER 10 SERIAL INTERFACE 10 (2)
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11.2 VFD Controller/Driver Configur
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(2) Display mode register 1 (DSPM1)
Page 111 and 112: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 113 and 114: CHAPTER 11 VFD CONTROLLER/DRIVER (2
Page 115 and 116: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 117 and 118: T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
Page 119 and 120: CHAPTER 11 VFD CONTROLLER/DRIVER By
Page 121 and 122: 12.1 Interrupt Function Types CHAPT
Page 123 and 124: (A) Internal non-maskable interrupt
Page 125 and 126: 12.3 Interrupt Function Control Reg
Page 127 and 128: CHAPTER 12 INTERRUPT FUNCTIONS (2)
Page 129 and 130: CHAPTER 12 INTERRUPT FUNCTIONS (4)
Page 131 and 132: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 133 and 134: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 135 and 136: INTxx CHAPTER 12 INTERRUPT FUNCTION
Page 137 and 138: 13.1 Standby Function and Configura
Page 139 and 140: 13.2 Operation of Standby Function
Page 141 and 142: CHAPTER 13 STANDBY FUNCTION (c) Rel
Page 143 and 144: CHAPTER 13 STANDBY FUNCTION (2) Rel
Page 145 and 146: CHAPTER 14 RESET FUNCTION The follo
Page 147 and 148: CHAPTER 14 RESET FUNCTION Table 14-
Page 149 and 150: 15.1 Flash Memory Programming VPP R
Page 151 and 152: CHAPTER 15 µPD78F9872 15.1.4 Examp
Page 153 and 154: CHAPTER 17 INSTRUCTION SET This cha
Page 155 and 156: 17.2 Operation List CHAPTER 17 INST
Page 157 and 158: CHAPTER 17 INSTRUCTION SET Mnemonic
Page 159 and 160: CHAPTER 17 INSTRUCTION SET Mnemonic
Page 161: CHAPTER 17 INSTRUCTION SET (2) 16-b
Page 165 and 166: A.1 Language Processing Software AP
Page 167 and 168: A.3.2 Software ID78K0S-NS Integrate
Page 169 and 170: C.1 Register Name Index (Alphabetic
Page 171 and 172: C.2 Register Symbol Index (Alphabet
Page 173: Facsimile Message From: Name Compan
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uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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