uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

14
LIST OF FIGURES (2/3)
Figure No. Title Page
7-3 8-Bit Timer Mode Control Register 80 Format ..................................................................................... 83
7-4 8-Bit Timer Mode Control Register 81 Format ..................................................................................... 84
7-5 Interval Timer Operation Timing ........................................................................................................... 86
8-1 Block Diagram of Watch Timer ............................................................................................................. 87
8-2 Watch Timer Mode Control Register Format ....................................................................................... 89
8-3 Watch Timer/Interval Timer Operation Timing ..................................................................................... 90
9-1 Block Diagram of Watchdog Timer ....................................................................................................... 92
9-2 Watchdog Timer Clock Select Register Format ................................................................................... 93
9-3 Watchdog Timer Mode Register Format .............................................................................................. 94
10-1 Block Diagram of Serial Interface 10 ................................................................................................... 98
10-2 Serial Operation Mode Register 10 Format ......................................................................................... 99
10-3 3-Wire Serial I/O Mode Timing ............................................................................................................. 103
11-1 Block Diagram of VFD Controller/Driver .............................................................................................. 105
11-2 Display Mode Register 0 Format .......................................................................................................... 106
11-3 Display Mode Register 1 Format .......................................................................................................... 107
11-4 Display Mode Register 2 Format .......................................................................................................... 108
11-5 Blanking Width of VFD Output Signal .................................................................................................. 109
11-6 Relationship Between Address Location of Display Data Memory and VFD Output
(with 25 VFD Output Pins and 16 Patterns) ........................................................................................ 110
11-7 Relationship Between Address Location of Display Data Memory and VFD Output
(with 20 VFD Output Pins and 9 Patterns) .......................................................................................... 111
11-8 Leakage Emission Because of Short Blanking Time........................................................................... 113
11-9 Leakage Emission Caused by CSG....................................................................................................... 114
11-10 Leakage Emission Caused by CSG....................................................................................................... 115
11-11 Total Power Dissipation PT (TA = –40 to +85°C) .................................................................................. 116
11-12 Relationship Between Display Data Memory Contents and VFD Output with
10 Segments-11 Digits Displayed ........................................................................................................ 118
12-1 Basic Configuration of Interrupt Function ............................................................................................ 121
12-2 Interrupt Request Flag Register Format .............................................................................................. 124
12-3 Interrupt Mask Flag Register Format ................................................................................................... 125
12-4 External Interrupt Mode Register 0 Format ......................................................................................... 126
12-5 Program Status Word Configuration .................................................................................................... 127
12-6 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement ......................... 129
12-7 Timing of Non-Maskable Interrupt Request Acknowledgement .......................................................... 129
12-8 Acknowledging Non-Maskable Interrupt Request ............................................................................... 129
12-9 Interrupt Acknowledgement Program Algorithm .................................................................................. 131
12-10 Interrupt Request Acknowledgement Timing (Example of MOV A,r) .................................................. 132
12-11 Interrupt Request Acknowledgement Timing
(When Interrupt Request Flag Is Generated at the Last Clock During Instruction Execution) ......... 132
Preliminary User’s Manual U14938EJ1V0UM