uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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138 CHAPTER 13 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three types of sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able to be acknowledged, vectored interrupt processing is performed. If the interrupt is disabled, the instruction at the next address is executed. Standby release signal Clock Operating mode Figure 13-2. Releasing HALT Mode by Interrupt HALT instruction HALT mode Oscillation Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. 2. The wait time is as follows: • When vectored interrupt processing is performed: 9 to 10 clocks • When vectored interrupt processing is not performed: 1 to 2 clocks (b) Releasing by non-maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed. Wait Wait Preliminary User’s Manual U14938EJ1V0UM Operating mode
CHAPTER 13 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 13-3. Releasing HALT Mode by RESET Input Remark fX: Main system clock oscillation frequency Table 13-2. Operation After Release of HALT Mode Releasing Source MK×× IE Operation Maskable interrupt request 0 0 Executes next address instruction 0 1 Executes interrupt processing 1 × Retains HALT mode Non-maskable interrupt request — × Executes interrupt processing RESET input — — Reset processing ×: don’t care RESET signal Clock Operating mode HALT instruction HALT mode Reset period Wait Oscillation stabilization wait status Oscillation stop Oscillation Oscillation Operating mode Preliminary User’s Manual U14938EJ1V0UM 139
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To our customers, Old Company Name
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Preliminary User’s Manual µPD789
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1 NOTES FOR CMOS DEVICES PRECAUTION
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Regional Information Some informati
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Documents Related to Devices Docume
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CONTENTS CHAPTER 1 GENERAL ........
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CHAPTER 8 WATCH TIMER .............
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LIST OF FIGURES (1/3) Figure No. Ti
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LIST OF FIGURES (3/3) Figure No. Ti
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LIST OF TABLES (2/2) Table No. Titl
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1.4 Pin Configuration (Top View)
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CHAPTER 1 GENERAL The major functio
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An outline of the timer is shown be
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(2) Non-port pins CHAPTER 2 PIN FUN
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CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
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CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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Data memory space Program memory sp
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FE20H
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3.2 Processor Registers CHAPTER 3 C
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CHAPTER 3 CPU ARCHITECTURE (3) Stac
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CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
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3.3 Instruction Address Addressing
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3.3.3 Table indirect addressing CHA
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3.4.2 Short direct addressing CHAPT
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3.4.4 Register addressing CHAPTER 3
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3.4.6 Based addressing CHAPTER 3 CP
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CHAPTER 4 PORT FUNCTIONS Table 4-1.
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CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
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Internal bus WRPUB2 RD WRPORT WRPM
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CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
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4.3 Port Function Control Registers
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4.4 Operation of Port Functions CHA
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XT1 XT2 X1 X2 Internal bus FRC SCC
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CHAPTER 5 CLOCK GENERATOR (2) Subos
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CHAPTER 5 CLOCK GENERATOR Figure 5-
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5.5 Clock Generator Operation CHAPT
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CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
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CHAPTER 6 8-BIT REMOTE CONTROL TIME
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CHAPTER 6 8-BIT REMOTE CONTROL TIME
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7.2 8-Bit Timer Configuration The 8
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7.3 Registers Controlling 8-Bit Tim
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7.4 8-Bit Timer Operation CHAPTER 7
Page 89 and 90: 8.1 Watch Timer Functions The watch
Page 91 and 92: WTM CHAPTER 8 WATCH TIMER Figure 8-
Page 93 and 94: CHAPTER 9 WATCHDOG TIMER The watchd
Page 95 and 96: 9.3 Registers Controlling Watchdog
Page 97 and 98: 9.4 Watchdog Timer Operation CHAPTE
Page 99 and 100: 10.1 Serial Interface 10 Functions
Page 101 and 102: 10.3 Register Controlling Serial In
Page 103 and 104: 10.4 Serial Interface 10 Operation
Page 105 and 106: CHAPTER 10 SERIAL INTERFACE 10 (2)
Page 107 and 108: 11.2 VFD Controller/Driver Configur
Page 109 and 110: (2) Display mode register 1 (DSPM1)
Page 111 and 112: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 113 and 114: CHAPTER 11 VFD CONTROLLER/DRIVER (2
Page 115 and 116: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 117 and 118: T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
Page 119 and 120: CHAPTER 11 VFD CONTROLLER/DRIVER By
Page 121 and 122: 12.1 Interrupt Function Types CHAPT
Page 123 and 124: (A) Internal non-maskable interrupt
Page 125 and 126: 12.3 Interrupt Function Control Reg
Page 127 and 128: CHAPTER 12 INTERRUPT FUNCTIONS (2)
Page 129 and 130: CHAPTER 12 INTERRUPT FUNCTIONS (4)
Page 131 and 132: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 133 and 134: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 135 and 136: INTxx CHAPTER 12 INTERRUPT FUNCTION
Page 137 and 138: 13.1 Standby Function and Configura
Page 139: 13.2 Operation of Standby Function
Page 143 and 144: CHAPTER 13 STANDBY FUNCTION (2) Rel
Page 145 and 146: CHAPTER 14 RESET FUNCTION The follo
Page 147 and 148: CHAPTER 14 RESET FUNCTION Table 14-
Page 149 and 150: 15.1 Flash Memory Programming VPP R
Page 151 and 152: CHAPTER 15 µPD78F9872 15.1.4 Examp
Page 153 and 154: CHAPTER 17 INSTRUCTION SET This cha
Page 155 and 156: 17.2 Operation List CHAPTER 17 INST
Page 157 and 158: CHAPTER 17 INSTRUCTION SET Mnemonic
Page 159 and 160: CHAPTER 17 INSTRUCTION SET Mnemonic
Page 161 and 162: CHAPTER 17 INSTRUCTION SET (2) 16-b
Page 163 and 164: APPENDIX A DEVELOPMENT TOOLS The fo
Page 165 and 166: A.1 Language Processing Software AP
Page 167 and 168: A.3.2 Software ID78K0S-NS Integrate
Page 169 and 170: C.1 Register Name Index (Alphabetic
Page 171 and 172: C.2 Register Symbol Index (Alphabet
Page 173: Facsimile Message From: Name Compan
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uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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