uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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12 13.1.1 Standby function ..................................................................................................................... 135 13.1.2 Register controlling standby function .................................................................................... 136 13.2 Operation of Standby Function...................................................................................... 137 13.2.1 HALT mode ............................................................................................................................. 137 13.2.2 STOP mode ............................................................................................................................ 140 CHAPTER 14 RESET FUNCTION ................................................................................................... 143 CHAPTER 15 µPD78F9872 .............................................................................................................. 146 15.1 Flash Memory Programming .......................................................................................... 147 15.1.1 Selecting communication mode ............................................................................................. 147 15.1.2 Function of flash memory programming................................................................................ 148 15.1.3 Flashpro III connection example ........................................................................................... 148 15.1.4 Example of settings for Flashpro III (PG-FP3) ....................................................................... 149 CHAPTER 16 MASK OPTION (MASK ROM VERSION) ................................................................ 150 CHAPTER 17 INSTRUCTION SET .................................................................................................. 151 17.1 Operation........................................................................................................................... 151 17.1.1 Operand identifiers and description methods ....................................................................... 151 17.1.2 Description of “operation” column ......................................................................................... 152 17.1.3 Description of “flag operation” column .................................................................................. 152 17.2 Operation List ................................................................................................................... 153 17.3 Instructions Listed by Addressing Type....................................................................... 158 APPENDIX A DEVELOPMENT TOOLS ........................................................................................... 161 A.1 Language Processing Software ...................................................................................... 163 A.2 Flash Memory Writing Tools ............................................................................................ 164 A.3 Debugging Tools................................................................................................................ 164 A.3.1 Hardware .................................................................................................................................. 164 A.3.2 Software ................................................................................................................................... 165 APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 166 APPENDIX C REGISTER INDEX ...................................................................................................... 167 C.1 Register Name Index (Alphabetic Order) ....................................................................... 167 C.2 Register Symbol Index (Alphabetic Order) .................................................................... 169 Preliminary User’s Manual U14938EJ1V0UM
LIST OF FIGURES (1/3) Figure No. Title Page 2-1 Pin I/O Circuits ...................................................................................................................................... 30 3-1 Memory Map (µPD789870) .................................................................................................................. 31 3-2 Memory Map (µPD789871) .................................................................................................................. 32 3-3 Memory Map (µPD78F9872) ................................................................................................................ 33 3-4 Data Memory Addressing (µPD789870) .............................................................................................. 36 3-5 Data Memory Addressing (µPD789871) .............................................................................................. 37 3-6 Data Memory Addressing (µPD78F9872) ............................................................................................ 38 3-7 Program Counter Configuration ........................................................................................................... 39 3-8 Program Status Word Configuration .................................................................................................... 39 3-9 Stack Pointer Configuration .................................................................................................................. 41 3-10 Data to Be Saved to Stack Memory ..................................................................................................... 41 3-11 Data to Be Restored from Stack Memory ............................................................................................ 41 3-12 General-Purpose Register Configuration ............................................................................................. 42 4-1 Port Types ............................................................................................................................................. 54 4-2 Block Diagram of P00 to P07 ............................................................................................................... 56 4-3 Block Diagram of P10 to P12 ............................................................................................................... 57 4-4 Block Diagram of P20 ........................................................................................................................... 58 4-5 Block Diagram of P21 ........................................................................................................................... 59 4-6 Block Diagram of P22 to P25 ............................................................................................................... 60 4-7 Block Diagram of P80 to P87 (µPD789870, 789871) ......................................................................... 61 4-8 Block Diagram of P80 to P87 (µPD78F9872) ...................................................................................... 61 4-9 Block Diagram of P90 to P97 (µPD789870, 789871) ......................................................................... 62 4-10 Block Diagram of P90 to P97 (µPD78F9872) ...................................................................................... 62 4-11 Port Mode Register Format .................................................................................................................. 64 4-12 Pull-Up Resistor Option Register 0 Format ......................................................................................... 64 4-13 Pull-Up Resistor Option Register B2 Format ....................................................................................... 64 5-1 Block Diagram of Clock Generator....................................................................................................... 67 5-2 Processor Clock Control Register Format ........................................................................................... 68 5-3 Suboscillation Mode Register Format .................................................................................................. 69 5-4 Subclock Control Register Format ....................................................................................................... 69 5-5 External Circuit of Main System Clock Oscillator ................................................................................ 70 5-6 External Circuit of Subsystem Clock Oscillator ................................................................................... 70 5-7 Examples of Incorrect Resonator Connection ..................................................................................... 71 5-8 Switching Between System Clock and CPU Clock ............................................................................. 75 6-1 Block Diagram of 8-Bit Remote Control Timer .................................................................................... 76 6-2 Remote Control Timer Control Register 50 Format............................................................................. 77 6-3 Pulse Width Measurement Timing........................................................................................................ 78 7-1 Block Diagram of 8-Bit Timer 80 .......................................................................................................... 81 7-2 Block Diagram of 8-Bit Timer 81 .......................................................................................................... 82 Preliminary User’s Manual U14938EJ1V0UM 13
Page 1 and 2: To our customers, Old Company Name
Page 3 and 4: Preliminary User’s Manual µPD789
Page 5 and 6: 1 NOTES FOR CMOS DEVICES PRECAUTION
Page 7 and 8: Regional Information Some informati
Page 9 and 10: Documents Related to Devices Docume
Page 11 and 12: CONTENTS CHAPTER 1 GENERAL ........
Page 13: CHAPTER 8 WATCH TIMER .............
Page 17 and 18: LIST OF FIGURES (3/3) Figure No. Ti
Page 19 and 20: LIST OF TABLES (2/2) Table No. Titl
Page 21 and 22: 1.4 Pin Configuration (Top View)
Page 23 and 24: CHAPTER 1 GENERAL The major functio
Page 25 and 26: An outline of the timer is shown be
Page 27 and 28: (2) Non-port pins CHAPTER 2 PIN FUN
Page 29 and 30: CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
Page 31 and 32: CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
Page 33 and 34: 3.1 Memory Space CHAPTER 3 CPU ARCH
Page 35 and 36: Data memory space Program memory sp
Page 37 and 38: CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
Page 39 and 40: FFFFH FF20H FF1FH FF00H FEFFH FE20H
Page 41 and 42: 3.2 Processor Registers CHAPTER 3 C
Page 43 and 44: CHAPTER 3 CPU ARCHITECTURE (3) Stac
Page 45 and 46: CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
Page 47 and 48: 3.3 Instruction Address Addressing
Page 49 and 50: 3.3.3 Table indirect addressing CHA
Page 51 and 52: 3.4.2 Short direct addressing CHAPT
Page 53 and 54: 3.4.4 Register addressing CHAPTER 3
Page 55 and 56: 3.4.6 Based addressing CHAPTER 3 CP
Page 57 and 58: CHAPTER 4 PORT FUNCTIONS Table 4-1.
Page 59 and 60: CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
Page 61 and 62: Internal bus WRPUB2 RD WRPORT WRPM
Page 63 and 64: CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
Page 65 and 66:
4.3 Port Function Control Registers
Page 67 and 68:
4.4 Operation of Port Functions CHA
Page 69 and 70:
XT1 XT2 X1 X2 Internal bus FRC SCC
Page 71 and 72:
CHAPTER 5 CLOCK GENERATOR (2) Subos
Page 73 and 74:
CHAPTER 5 CLOCK GENERATOR Figure 5-
Page 75 and 76:
5.5 Clock Generator Operation CHAPT
Page 77 and 78:
CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
Page 79 and 80:
CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 81 and 82:
CHAPTER 6 8-BIT REMOTE CONTROL TIME
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7.2 8-Bit Timer Configuration The 8
Page 85 and 86:
7.3 Registers Controlling 8-Bit Tim
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7.4 8-Bit Timer Operation CHAPTER 7
Page 89 and 90:
8.1 Watch Timer Functions The watch
Page 91 and 92:
WTM CHAPTER 8 WATCH TIMER Figure 8-
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CHAPTER 9 WATCHDOG TIMER The watchd
Page 95 and 96:
9.3 Registers Controlling Watchdog
Page 97 and 98:
9.4 Watchdog Timer Operation CHAPTE
Page 99 and 100:
10.1 Serial Interface 10 Functions
Page 101 and 102:
10.3 Register Controlling Serial In
Page 103 and 104:
10.4 Serial Interface 10 Operation
Page 105 and 106:
CHAPTER 10 SERIAL INTERFACE 10 (2)
Page 107 and 108:
11.2 VFD Controller/Driver Configur
Page 109 and 110:
(2) Display mode register 1 (DSPM1)
Page 111 and 112:
CHAPTER 11 VFD CONTROLLER/DRIVER 11
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CHAPTER 11 VFD CONTROLLER/DRIVER (2
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CHAPTER 11 VFD CONTROLLER/DRIVER 11
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T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
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CHAPTER 11 VFD CONTROLLER/DRIVER By
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12.1 Interrupt Function Types CHAPT
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(A) Internal non-maskable interrupt
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12.3 Interrupt Function Control Reg
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CHAPTER 12 INTERRUPT FUNCTIONS (2)
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CHAPTER 12 INTERRUPT FUNCTIONS (4)
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CHAPTER 12 INTERRUPT FUNCTIONS Figu
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CHAPTER 12 INTERRUPT FUNCTIONS Figu
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INTxx CHAPTER 12 INTERRUPT FUNCTION
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13.1 Standby Function and Configura
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13.2 Operation of Standby Function
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CHAPTER 13 STANDBY FUNCTION (c) Rel
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CHAPTER 13 STANDBY FUNCTION (2) Rel
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CHAPTER 14 RESET FUNCTION The follo
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CHAPTER 14 RESET FUNCTION Table 14-
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15.1 Flash Memory Programming VPP R
Page 151 and 152:
CHAPTER 15 µPD78F9872 15.1.4 Examp
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CHAPTER 17 INSTRUCTION SET This cha
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17.2 Operation List CHAPTER 17 INST
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET (2) 16-b
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APPENDIX A DEVELOPMENT TOOLS The fo
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A.1 Language Processing Software AP
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A.3.2 Software ID78K0S-NS Integrate
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C.1 Register Name Index (Alphabetic
Page 171 and 172:
C.2 Register Symbol Index (Alphabet
Page 173:
Facsimile Message From: Name Compan
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uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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