uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
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CHAPTER 11 VFD CONTROLLER/DRIVER<br />
(2) With 20 VFD output pins and 9 patterns<br />
The addresses of the display data memory corresponding to the data output at each display timing (T0 to T8)<br />
are as shown in Figure 11-7 (for example, T0 = FA00H to FA02H, and T1 = FA03H to FA05H). When 20 VFD<br />
output pins (FIP0 to FIP19) are used, one block of display data consists of 3 bytes. VFD output pins 0 (FIP0)<br />
to 19 (FIP19) correspond to one block of display data sequentially, starting from the least significant bit toward<br />
the most significant bit.<br />
Figure 11-7. Relationship Between Address Location of Display Data Memory and VFD Output<br />
(with 20 VFD Output Pins and 9 Patterns)<br />
Address<br />
FA18H to FA1AH<br />
FA15H to FA17H<br />
FA09H to FA0BH<br />
FA06H to FA08H<br />
FA03H to FA05H<br />
FA00H to FA02H<br />
6BH<br />
64H<br />
17H<br />
10H<br />
09H<br />
02H<br />
19 16<br />
6AH<br />
63H<br />
16H<br />
0FH<br />
08H<br />
01H<br />
69H<br />
62H<br />
15H<br />
0EH<br />
07H<br />
00H<br />
7 0<br />
(VFD output pins)<br />
Preliminary User’s Manual U14938EJ1V0UM<br />
Display timing<br />
TKS<br />
T8<br />
T7<br />
T3<br />
T2<br />
T1<br />
T0<br />
111
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