uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM
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108<br />
CHAPTER 11 VFD CONTROLLER/DRIVER<br />
(3) Display mode register 2 (DSPM2)<br />
DSPM2 performs the following setting. It also indicates the status of the display timing/key scan.<br />
Symbol<br />
DSPM2<br />
• Insertion of key scan timing<br />
• Display cycle (TDSP)<br />
DSPM2 is set with a 1-bit or 8-bit memory manipulation instruction. However, only bit 7 (KSF) can be read by<br />
a 1-bit memory manipulation instruction.<br />
RESET input clears DSPM2 to 00H.<br />
7<br />
KSF<br />
6<br />
KSM<br />
Figure 11-4. Display Mode Register 2 Format<br />
KSF Status of key scan cycle<br />
0 Other than key scan cycle<br />
1 Key scan cycle<br />
5<br />
0<br />
4<br />
0<br />
KSM Key scan cycle insertion selection<br />
0 Not inserted<br />
1 Inserted<br />
FCYC1 FCYC0 Display cycle<br />
0 0 212 /fX (819 µs)<br />
0 1 211 /fX (410 µs)<br />
1 0 210 /fX (205 µs)<br />
1 1 Setting prohibited<br />
3<br />
0<br />
Cautions 1. Be sure to set bits 2 to 5 to 0.<br />
2. Do not write data to the display mode register 2 (DSPM2) when bit 7 (DSPEN) of the<br />
display mode register 0 (DSPM0) is 1.<br />
Remarks 1. fX: Main system clock oscillation frequency<br />
2. The parenthesized values apply to operation at fX = 5.0 MHz.<br />
2<br />
0<br />
Preliminary User’s Manual U14938EJ1V0UM<br />
1<br />
FCYC1<br />
0<br />
FCYC0<br />
Address<br />
FFA2H<br />
After reset<br />
00H<br />
R/W<br />
R/W
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