uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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100 (1) Operation stop mode CHAPTER 10 SERIAL INTERFACE 10 Table 10-2. Settings of Serial Interface 10 Operation Mode CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI10 P21/SO10 P20/SCK10 CSIE10 DIR10 CSCK10 Bit Clock Pin Function Pin Function Pin Function 0 × × × Note 1 × Note 1 × Note 1 × Note 1 × Note 1 × Note 1 – – P22 P21 P20 Other than above Setting prohibited (2) 3-wire serial I/O mode CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI10 P21/SO10 P20/SCK10 CSIE10 DIR10 CSCK10 Bit Clock Pin Function Pin Function Pin Function 1 0 0 1 Note 2 × Note 2 0 1 1 × MSB External SI10 Note 2 SO10 SCK10 input Preliminary User’s Manual U14938EJ1V0UM clock (CMOS output) 1 0 1 External SCK10 output 1 1 0 1 × LSB External SCK10 input 1 0 1 External clock SCK10 output clock clock Other than above Setting prohibited Notes 1. Can be used as port function. 2. If used only for transmission, can be used as P22 (CMOS I/O port). Remark ×: don’t care
10.4 Serial Interface 10 Operation CHAPTER 10 SERIAL INTERFACE 10 Serial interface 10 provides the following two types of modes. • Operation stop mode • 3-wire serial I/O mode 10.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operation mode register 10 (CSIM10). Serial operation mode register 10 (CSIM10) CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H. Symbol 6 5 4 3 2 1 0 Address After reset R/W CSIM10 CSIE10 0 TPS101 TPS100 0 DIR10 CSCK10 0 CSIE10 0 1 Operation stopped Operation enabled Caution Bits 0, 3, and 6 must be set to 0. Operation control in 3-wire serial I/O mode FF72H 00H R/W Preliminary User’s Manual U14938EJ1V0UM 101
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To our customers, Old Company Name
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Preliminary User’s Manual µPD789
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1 NOTES FOR CMOS DEVICES PRECAUTION
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Regional Information Some informati
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Documents Related to Devices Docume
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CONTENTS CHAPTER 1 GENERAL ........
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CHAPTER 8 WATCH TIMER .............
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LIST OF FIGURES (1/3) Figure No. Ti
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LIST OF FIGURES (3/3) Figure No. Ti
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LIST OF TABLES (2/2) Table No. Titl
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1.4 Pin Configuration (Top View)
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CHAPTER 1 GENERAL The major functio
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An outline of the timer is shown be
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(2) Non-port pins CHAPTER 2 PIN FUN
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CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
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CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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Data memory space Program memory sp
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FE20H
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3.2 Processor Registers CHAPTER 3 C
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CHAPTER 3 CPU ARCHITECTURE (3) Stac
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CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
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3.3 Instruction Address Addressing
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3.3.3 Table indirect addressing CHA
Page 51 and 52: 3.4.2 Short direct addressing CHAPT
Page 53 and 54: 3.4.4 Register addressing CHAPTER 3
Page 55 and 56: 3.4.6 Based addressing CHAPTER 3 CP
Page 57 and 58: CHAPTER 4 PORT FUNCTIONS Table 4-1.
Page 59 and 60: CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
Page 61 and 62: Internal bus WRPUB2 RD WRPORT WRPM
Page 63 and 64: CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
Page 65 and 66: 4.3 Port Function Control Registers
Page 67 and 68: 4.4 Operation of Port Functions CHA
Page 69 and 70: XT1 XT2 X1 X2 Internal bus FRC SCC
Page 71 and 72: CHAPTER 5 CLOCK GENERATOR (2) Subos
Page 73 and 74: CHAPTER 5 CLOCK GENERATOR Figure 5-
Page 75 and 76: 5.5 Clock Generator Operation CHAPT
Page 77 and 78: CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
Page 79 and 80: CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 81 and 82: CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 83 and 84: 7.2 8-Bit Timer Configuration The 8
Page 85 and 86: 7.3 Registers Controlling 8-Bit Tim
Page 87 and 88: 7.4 8-Bit Timer Operation CHAPTER 7
Page 89 and 90: 8.1 Watch Timer Functions The watch
Page 91 and 92: WTM CHAPTER 8 WATCH TIMER Figure 8-
Page 93 and 94: CHAPTER 9 WATCHDOG TIMER The watchd
Page 95 and 96: 9.3 Registers Controlling Watchdog
Page 97 and 98: 9.4 Watchdog Timer Operation CHAPTE
Page 99 and 100: 10.1 Serial Interface 10 Functions
Page 101: 10.3 Register Controlling Serial In
Page 105 and 106: CHAPTER 10 SERIAL INTERFACE 10 (2)
Page 107 and 108: 11.2 VFD Controller/Driver Configur
Page 109 and 110: (2) Display mode register 1 (DSPM1)
Page 111 and 112: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 113 and 114: CHAPTER 11 VFD CONTROLLER/DRIVER (2
Page 115 and 116: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 117 and 118: T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
Page 119 and 120: CHAPTER 11 VFD CONTROLLER/DRIVER By
Page 121 and 122: 12.1 Interrupt Function Types CHAPT
Page 123 and 124: (A) Internal non-maskable interrupt
Page 125 and 126: 12.3 Interrupt Function Control Reg
Page 127 and 128: CHAPTER 12 INTERRUPT FUNCTIONS (2)
Page 129 and 130: CHAPTER 12 INTERRUPT FUNCTIONS (4)
Page 131 and 132: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 133 and 134: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 135 and 136: INTxx CHAPTER 12 INTERRUPT FUNCTION
Page 137 and 138: 13.1 Standby Function and Configura
Page 139 and 140: 13.2 Operation of Standby Function
Page 141 and 142: CHAPTER 13 STANDBY FUNCTION (c) Rel
Page 143 and 144: CHAPTER 13 STANDBY FUNCTION (2) Rel
Page 145 and 146: CHAPTER 14 RESET FUNCTION The follo
Page 147 and 148: CHAPTER 14 RESET FUNCTION Table 14-
Page 149 and 150: 15.1 Flash Memory Programming VPP R
Page 151 and 152: CHAPTER 15 µPD78F9872 15.1.4 Examp
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CHAPTER 17 INSTRUCTION SET This cha
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17.2 Operation List CHAPTER 17 INST
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET (2) 16-b
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APPENDIX A DEVELOPMENT TOOLS The fo
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A.1 Language Processing Software AP
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A.3.2 Software ID78K0S-NS Integrate
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C.1 Register Name Index (Alphabetic
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C.2 Register Symbol Index (Alphabet
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Facsimile Message From: Name Compan
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uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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