uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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98 Preliminary User’s Manual U14938EJ1V0UM SI10/P22 SO10/P21 SCK10/P20 Figure 10-1. Block Diagram of Serial Interface 10 CSIE10 TPS100 TPS101 DIR10 Internal bus Serial operation mode register 10 (CSIM10) CSCK10 Clock control circuit Transmit/receive shift register 10 (SIO10) Serial clock counter F/F Selector Selector Interrupt request generator fX/2 2 fX/2 3 fX/2 4 fX/2 5 INTCSI10 CHAPTER 10 SERIAL INTERFACE 10
10.3 Register Controlling Serial Interface 10 CHAPTER 10 SERIAL INTERFACE 10 The following register is used to control serial interface 10. • Serial operation mode register 10 (CSIM10) (1) Serial operation mode register 10 (CSIM10) This register is used to control serial interface 10 operation and set the serial clock and start bit. CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H. Figure 10-2. Serial Operation Mode Register 10 Format Symbol 6 5 4 3 2 1 0 Address After reset R/W CSIM10 CSIE10 0 TPS101TPS100 0 DIR10 CSCK10 0 CSIE10 0 1 TPS101 TPS100 0 0 1 1 DIR10 0 1 CSCK10 0 1 Operation stopped Operation enabled 0 1 0 1 MSB LSB fX/2 2 (1.25 MHz) fX/2 3 (625 kHz) fX/2 4 (313 kHz) fX/2 5 (157 kHz) Input clock to SCK10 pin from external Caution <strong>Bit</strong>s 0, 3, and 6 must be set to 0. Operation control in 3-wire serial I/O mode FF72H 00H R/W Count clock selection during operation enable in 3-wire serial I/O mode Internal clock selected by TPS100, TPS101 Start bit specification Clock selection in 3-wire serial I/O mode Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 50 MHz. Preliminary User’s Manual U14938EJ1V0UM 99
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To our customers, Old Company Name
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Preliminary User’s Manual µPD789
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1 NOTES FOR CMOS DEVICES PRECAUTION
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Regional Information Some informati
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Documents Related to Devices Docume
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CONTENTS CHAPTER 1 GENERAL ........
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CHAPTER 8 WATCH TIMER .............
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LIST OF FIGURES (1/3) Figure No. Ti
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LIST OF FIGURES (3/3) Figure No. Ti
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LIST OF TABLES (2/2) Table No. Titl
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1.4 Pin Configuration (Top View)
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CHAPTER 1 GENERAL The major functio
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An outline of the timer is shown be
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(2) Non-port pins CHAPTER 2 PIN FUN
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CHAPTER 2 PIN FUNCTIONS 2.2.5 P90 t
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CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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Data memory space Program memory sp
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FE20H
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3.2 Processor Registers CHAPTER 3 C
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CHAPTER 3 CPU ARCHITECTURE (3) Stac
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CHAPTER 3 CPU ARCHITECTURE 3.2.3 Sp
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3.3 Instruction Address Addressing
Page 49 and 50: 3.3.3 Table indirect addressing CHA
Page 51 and 52: 3.4.2 Short direct addressing CHAPT
Page 53 and 54: 3.4.4 Register addressing CHAPTER 3
Page 55 and 56: 3.4.6 Based addressing CHAPTER 3 CP
Page 57 and 58: CHAPTER 4 PORT FUNCTIONS Table 4-1.
Page 59 and 60: CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
Page 61 and 62: Internal bus WRPUB2 RD WRPORT WRPM
Page 63 and 64: CHAPTER 4 PORT FUNCTIONS 4.2.4 Port
Page 65 and 66: 4.3 Port Function Control Registers
Page 67 and 68: 4.4 Operation of Port Functions CHA
Page 69 and 70: XT1 XT2 X1 X2 Internal bus FRC SCC
Page 71 and 72: CHAPTER 5 CLOCK GENERATOR (2) Subos
Page 73 and 74: CHAPTER 5 CLOCK GENERATOR Figure 5-
Page 75 and 76: 5.5 Clock Generator Operation CHAPT
Page 77 and 78: CHAPTER 5 CLOCK GENERATOR 5.6.2 Swi
Page 79 and 80: CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 81 and 82: CHAPTER 6 8-BIT REMOTE CONTROL TIME
Page 83 and 84: 7.2 8-Bit Timer Configuration The 8
Page 85 and 86: 7.3 Registers Controlling 8-Bit Tim
Page 87 and 88: 7.4 8-Bit Timer Operation CHAPTER 7
Page 89 and 90: 8.1 Watch Timer Functions The watch
Page 91 and 92: WTM CHAPTER 8 WATCH TIMER Figure 8-
Page 93 and 94: CHAPTER 9 WATCHDOG TIMER The watchd
Page 95 and 96: 9.3 Registers Controlling Watchdog
Page 97 and 98: 9.4 Watchdog Timer Operation CHAPTE
Page 99: 10.1 Serial Interface 10 Functions
Page 103 and 104: 10.4 Serial Interface 10 Operation
Page 105 and 106: CHAPTER 10 SERIAL INTERFACE 10 (2)
Page 107 and 108: 11.2 VFD Controller/Driver Configur
Page 109 and 110: (2) Display mode register 1 (DSPM1)
Page 111 and 112: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 113 and 114: CHAPTER 11 VFD CONTROLLER/DRIVER (2
Page 115 and 116: CHAPTER 11 VFD CONTROLLER/DRIVER 11
Page 117 and 118: T0 T1 S0 CHAPTER 11 VFD CONTROLLER/
Page 119 and 120: CHAPTER 11 VFD CONTROLLER/DRIVER By
Page 121 and 122: 12.1 Interrupt Function Types CHAPT
Page 123 and 124: (A) Internal non-maskable interrupt
Page 125 and 126: 12.3 Interrupt Function Control Reg
Page 127 and 128: CHAPTER 12 INTERRUPT FUNCTIONS (2)
Page 129 and 130: CHAPTER 12 INTERRUPT FUNCTIONS (4)
Page 131 and 132: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 133 and 134: CHAPTER 12 INTERRUPT FUNCTIONS Figu
Page 135 and 136: INTxx CHAPTER 12 INTERRUPT FUNCTION
Page 137 and 138: 13.1 Standby Function and Configura
Page 139 and 140: 13.2 Operation of Standby Function
Page 141 and 142: CHAPTER 13 STANDBY FUNCTION (c) Rel
Page 143 and 144: CHAPTER 13 STANDBY FUNCTION (2) Rel
Page 145 and 146: CHAPTER 14 RESET FUNCTION The follo
Page 147 and 148: CHAPTER 14 RESET FUNCTION Table 14-
Page 149 and 150: 15.1 Flash Memory Programming VPP R
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CHAPTER 15 µPD78F9872 15.1.4 Examp
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CHAPTER 17 INSTRUCTION SET This cha
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17.2 Operation List CHAPTER 17 INST
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET Mnemonic
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CHAPTER 17 INSTRUCTION SET (2) 16-b
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APPENDIX A DEVELOPMENT TOOLS The fo
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A.1 Language Processing Software AP
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A.3.2 Software ID78K0S-NS Integrate
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C.1 Register Name Index (Alphabetic
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C.2 Register Symbol Index (Alphabet
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Facsimile Message From: Name Compan
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uPD789871 Subseries 8-Bit Single-Chip Microcontrollers PUM

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