uPD780065 Subseries PUM - Renesas Electronics

CHAPTER 5 CLOCK GENERATOR
Cautions 1. When using the main system clock oscillator and a subsystem clock oscillator, carry out
wiring in the broken line area in Figures 5-4 and 5-5 to prevent any effects from wiring
capacitance.
• Minimize the wiring length.
• Do not allow wiring to intersect with other signal lines. Do not route the wiring in the
vicinity of a line through which a high-fluctuating current flows.
• Always keep the ground of the capacitor of the oscillation circuit at the same potential as
VSS1. Do not ground a capacitor to a ground pattern where high-current flows.
• Do not fetch signals from the oscillator.
Take special note of the fact that the subsystem clock oscillator is a circuit with low-level
amplification so that current consumption is maintained at low levels.
Figure 5-6 shows examples of incorrect oscillator connection.
Figure 5-6. Examples of Incorrect Oscillator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
IC X1 X2
IC X1 X2
VSS1 VSS1
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert
resistors in series on the side of XT2.
Preliminary User’s Manual U13420EJ2V0UM00
PORTn
(n = 0, 2 to 9)
95