uPD780065 Subseries PUM - Renesas Electronics

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3.4.3 Direct addressing 64 CHAPTER 3 CPU ARCHITECTURE [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H [Illustration] 7 Operation code 1 0 0 0 1 1 1 0 OP code OP code addr16 (lower) addr16 (upper) 0 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Memory Preliminary User’s Manual U13420EJ2V0UM00
3.4.4 Short direct addressing CHAPTER 3 CPU ARCHITECTURE [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. If the SFR area (FF00H to FF1FH) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration] on the next page. [Operand format] Identifier Description saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immediate data (even address only) Preliminary User’s Manual U13420EJ2V0UM00 65
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To our customers, Old Company Name
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Preliminary User’s Manual μPD780
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NOTES FOR CMOS DEVICES 1 PRECAUTION
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NEC Electronics Inc. (U.S.) Santa C
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INTRODUCTION Readers This manual ha
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• Related documents for embedded
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CONTENTS CHAPTER 1 OUTLINE ........
Page 15 and 16: 5.5 Clock Generator Operations ....
Page 17 and 18: CHAPTER 15 SERIAL INTERFACE (SIO30)
Page 19 and 20: LIST OF FIGURES (1/5) Figure No. Ti
Page 25 and 26: LIST OF TABLES (1/2) Table No. Titl
Page 27 and 28: 1.1 Features • Internal Memory CH
Page 29 and 30: 1.4 Pin Configuration (Top View)
Page 31 and 32: 1.5 78K/0 Series Lineup CHAPTER 1 O
Page 33 and 34: 1.6 Block Diagram TI00/TO0/P20 TI01
Page 35 and 36: 2.1 Pin Functions (1) Port Pins (1/
Page 37 and 38: (2) Non-port Pins (2/2) CHAPTER 2 P
Page 39 and 40: CHAPTER 2 PIN FUNCTION 2.2.3 P30 to
Page 41 and 42: CHAPTER 2 PIN FUNCTION 2.2.8 P80 to
Page 43 and 44: CHAPTER 2 PIN FUNCTION 2.3 Pin I/O
Page 45 and 46: 3.1 Memory Space CHAPTER 3 CPU ARCH
Page 47 and 48: CHAPTER 3 CPU ARCHITECTURE 3.1.1 In
Page 49 and 50: CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
Page 51 and 52: FFFFH FF20H FF1FH FF00H FEFFH FEE0H
Page 53 and 54: CHAPTER 3 CPU ARCHITECTURE (a) Inte
Page 55 and 56: CHAPTER 3 CPU ARCHITECTURE 3.2.2 Ge
Page 57 and 58: CHAPTER 3 CPU ARCHITECTURE Table 3-
Page 59 and 60: CHAPTER 3 CPU ARCHITECTURE Table 3-
Page 61 and 62: 3.3.2 Immediate addressing CHAPTER
Page 63 and 64: 3.3.4 Register addressing CHAPTER 3
Page 65: 3.4.2 Register addressing CHAPTER 3
Page 69 and 70: 3.4.5 Special-function register (SF
Page 71 and 72: 3.4.7 Based addressing CHAPTER 3 CP
Page 73 and 74: 4.1 Port Functions CHAPTER 4 PORT F
Page 75 and 76: 4.2 Port Configuration A port consi
Page 77 and 78: CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
Page 83 and 84: Internal bus WRPU RD WRPORT WRPM PU
Page 87 and 88: CHAPTER 4 PORT FUNCTIONS Figure 4-1
Page 89 and 90: CHAPTER 4 PORT FUNCTIONS Figure 4-1
Page 91 and 92: 5.1 Clock Generator Functions CHAPT
Page 93 and 94: 5.3 Clock Generator Control Registe
Page 95 and 96: CHAPTER 5 CLOCK GENERATOR The faste
Page 97 and 98: CHAPTER 5 CLOCK GENERATOR Cautions
Page 99 and 100: CHAPTER 5 CLOCK GENERATOR 5.4.3 Sca
Page 101 and 102: CHAPTER 5 CLOCK GENERATOR 5.5.1 Mai
Page 103 and 104: Set Value before Switchover CHAPTER
Page 105 and 106: CHAPTER 6 16-BIT TIMER/EVENT COUNTE
Page 107 and 108: TI01/P21 fX/2 3 TI00/TO0/P20 Captur
Page 111 and 112: TMC03 TMC02 TMC01 CHAPTER 6 16-BIT
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TI00/TO0/P20 Count clock TM0 count
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CHAPTER 6 16-BIT TIMER/EVENT COUNTE
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CRC0 CHAPTER 6 16-BIT TIMER/EVENT C
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fX/2 3 Valid edge of TI00 TI00 pin
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Count clock TM0 count value CR00 IN
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7.1 8-Bit Timer/Event Counter Funct
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7.2 8-Bit Timer/Event Counter Confi
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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Count clock TM5n count value CR5n T
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n = 0, 1 Count clock TM5 CR5n TCE5n
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Count clock n = 0, 1 TM5n CR5n TCE5
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8.1 Watch Timer Functions The watch
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8.3 Register to Control Watch Timer
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Count clock fW/2 9 Watch timer inte
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9.1 Watchdog Timer Functions The wa
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9.2 Watchdog Timer Configuration CH
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CHAPTER 9 WATCHDOG TIMER (2) Watchd
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9.4 Watchdog Timer Operations CHAPT
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CHAPTER 10 CLOCK OUTPUT CONTROL CIR
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Address: FF40H After reset: 00H R/W
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11.1 A/D Converter Functions CHAPTE
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CHAPTER 11 A/D CONVERTER (6) ANI0 t
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CHAPTER 11 A/D CONVERTER (2) Analog
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A/D converter operation SAR ADCR0 I
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CHAPTER 11 A/D CONVERTER 11.4.3 A/D
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CHAPTER 11 A/D CONVERTER (4) Noise
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CHAPTER 12 SERIAL INTERFACE OUTLINE
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13.1 Serial Interface (UART0) Funct
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CHAPTER 13 SERIAL INTERFACE (UART0)
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13.4 Serial Interface (UART0) Opera
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Address: FFA0H After reset: 00H R/W
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(2) Communication operations CHAPTE
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14.1 Serial Interface (SIO1) Functi
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Figure 14-1. Block Diagram of Seria
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14.3 Serial Interface (SIO1) Contro
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CHAPTER 14 SERIAL INTERFACE (SIO1)
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Symbol Address: FF68H After reset:
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Symbol Address: FF6BH After reset:
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(3) Communication operation CHAPTER
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SCK1 CHAPTER 14 SERIAL INTERFACE (S
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SCK1 SO1 SI1 BUSY CSIIF1 TRF0 CHAPT
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15.1 Serial Interface (SIO30) Funct
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16.1 Serial Interface (SIO31) Funct
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17.1 Interrupt Function Types CHAPT
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(A) Internal non-maskable interrupt
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17.3 Interrupt Function Control Reg
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CHAPTER 17 INTERRUPT FUNCTIONS (2)
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CHAPTER 17 INTERRUPT FUNCTIONS (4)
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17.4 Interrupt Servicing Operations
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CHAPTER 17 INTERRUPT FUNCTIONS Figu
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CHAPTER 17 INTERRUPT FUNCTIONS 17.4
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CHAPTER 18 EXTERNAL DEVICE EXPANSIO
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ASTB RD AD0 to AD7 A8 to A15 ASTB R
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ASTB RD WR AD0 to AD7 A8 to A15 AST
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19.1 Standby Function and Configura
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19.2 Standby Function Operations 19
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CHAPTER 19 STANDBY FUNCTION (c) Cle
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CHAPTER 19 STANDBY FUNCTION (2) STO
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20.1 Reset Function CHAPTER 20 RESE
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CHAPTER 20 RESET FUNCTION Table 20-
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CHAPTER 21 μPD78F0066 The μPD78F0
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CHAPTER 21 μPD78F0066 21.2 Interna
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CHAPTER 21 μPD78F0066 21.3.2 Flash
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CHAPTER 22 INSTRUCTION SET This cha
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CHAPTER 22 INSTRUCTION SET 22.1.2 D
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Instruction Group 16-bit data trans
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Instruction Group 8-bit operation C
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Second O
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CHAPTER 22 INSTRUCTION SET (4) Call
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APPENDIX A DEVELOPMENT TOOLS The fo
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(2) When using the in-circuit emula
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APPENDIX A DEVELOPMENT TOOLS Remark
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A.3.1 Hardware (2/2) (2) When using
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A.3.2 Software (2/2) ID78K0-NS Inte
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APPENDIX A DEVELOPMENT TOOLS Conver
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APPENDIX B EMBEDDED SOFTWARE For ef
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Real-Time OS (2/2) APPENDIX B EMBED
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APPENDIX C REGISTER INDEX C.1 Regis
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16-bit timer/counter 0 (TM0) … 10
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[P] P0: Port 0 … 73 P2: Port 2
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