uPD780065 Subseries PUM - Renesas Electronics

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250 CHAPTER 14 SERIAL INTERFACE (SIO1) (5) Timing of interrupt request signal generation The interrupt request signal is generated in synchronization with the timing shown in Table 14-2. Table 14-2. Timing of Interrupt Request Signal Generation Operating Mode Timing of Interrupt Request Signal Single mode Master mode 10th serial clock at end of transfer Slave mode 8th serial clock at end of transfer Repetitive transmit mode Not generated If bit shift occurs during transmission/reception 8th serial clock (6) Interval time of automatic transmission/reception Because read/write to/from the buffer RAM using the automatic transmit/receive function is performed asynchronously with CPU processing, the interval time is dependent on the CPU processing of the timing of the eighth rising of the serial clock and the set value of the automatic data transmit/receive interval specification register (ADTI0). Whether the interval time is dependent on ADTI0 is selected by setting of the bit 7 (ADTI07) of ADTI0. If ADTI07 is reset to 0, the interval time is 2/fSCK. If ADTI07 is set to 1, the interval time determined by the set contents of ADTI0 or interval time (2/fSCK) according to CPU processing is selected, whichever is is greater. Figure 14-23 shows the interval time of automatic transmission/reception Remark fSCK: Serial clock frequency SCK1 SO1 SI1 CSIIF1 D7 Figure 14-23. Interval Time of Automatic Transmission/Reception Interval D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 The following expression must be satisfied to access the buffer RAM. 1 transfer cycle + interval time ≥ Read access + Write access + CPU buffer RAM access (time) In the case of a “high-speed CPU & low-speed SCKNote ”, the interval time is not necessary. In the case of a “low-speed CPU & high-speed SCKNote ”, the interval time is necessary. In this case, make sure that a sufficient interval time elapses by using the automatic data transmit/receive interval specification register (ADTI0), so that the above expression is satisfied. Note The speeds of the CPU clock and SCK differ depending on the type of CPU core. Preliminary User’s Manual U13420EJ2V0UM00
15.1 Serial Interface (SIO30) Functions CHAPTER 15 SERIAL INTERFACE (SIO30) The serial interface (SIO30) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 15.4.1 Operation stop mode. (2) 2-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using two lines: a serial clock line (SCK30) and serial data input/output line (SDIO30). The first bit of the serial transferred 8-bit data is fixed as the MSB. 2-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clock-synchronous serial interface, or a display controller, etc. For details see 15.4.2 2-wire serial I/O mode. Figure 15-1 shows a block diagram of the serial interface (SIO30). SDIO30/P75 Figure 15-1. Serial Interface (SIO30) Block Diagram Internal bus Interrupt SCK30/P74 Serial clock request signal INTCSI30 counter generator Serial clock control circuit Preliminary User’s Manual U13420EJ2V0UM00 8 Serial I/O shift register 30 (SIO30) Selector fX/2 5 fX/2 6 fX/2 7 251
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To our customers, Old Company Name
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Preliminary User’s Manual μPD780
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NOTES FOR CMOS DEVICES 1 PRECAUTION
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NEC Electronics Inc. (U.S.) Santa C
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INTRODUCTION Readers This manual ha
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• Related documents for embedded
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CONTENTS CHAPTER 1 OUTLINE ........
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5.5 Clock Generator Operations ....
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CHAPTER 15 SERIAL INTERFACE (SIO30)
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LIST OF FIGURES (1/5) Figure No. Ti
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LIST OF TABLES (1/2) Table No. Titl
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1.1 Features • Internal Memory CH
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1.4 Pin Configuration (Top View)
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1.5 78K/0 Series Lineup CHAPTER 1 O
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1.6 Block Diagram TI00/TO0/P20 TI01
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2.1 Pin Functions (1) Port Pins (1/
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(2) Non-port Pins (2/2) CHAPTER 2 P
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CHAPTER 2 PIN FUNCTION 2.2.3 P30 to
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CHAPTER 2 PIN FUNCTION 2.2.8 P80 to
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CHAPTER 2 PIN FUNCTION 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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CHAPTER 3 CPU ARCHITECTURE 3.1.1 In
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FEE0H
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CHAPTER 3 CPU ARCHITECTURE (a) Inte
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CHAPTER 3 CPU ARCHITECTURE 3.2.2 Ge
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CHAPTER 3 CPU ARCHITECTURE Table 3-
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CHAPTER 3 CPU ARCHITECTURE Table 3-
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3.3.2 Immediate addressing CHAPTER
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3.3.4 Register addressing CHAPTER 3
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3.4.2 Register addressing CHAPTER 3
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3.4.4 Short direct addressing CHAPT
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3.4.5 Special-function register (SF
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3.4.7 Based addressing CHAPTER 3 CP
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4.1 Port Functions CHAPTER 4 PORT F
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4.2 Port Configuration A port consi
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CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
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Internal bus WRPU RD WRPORT WRPM PU
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CHAPTER 4 PORT FUNCTIONS Figure 4-1
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CHAPTER 4 PORT FUNCTIONS Figure 4-1
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5.1 Clock Generator Functions CHAPT
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5.3 Clock Generator Control Registe
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CHAPTER 5 CLOCK GENERATOR The faste
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CHAPTER 5 CLOCK GENERATOR Cautions
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CHAPTER 5 CLOCK GENERATOR 5.4.3 Sca
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CHAPTER 5 CLOCK GENERATOR 5.5.1 Mai
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Set Value before Switchover CHAPTER
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CHAPTER 6 16-BIT TIMER/EVENT COUNTE
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TI01/P21 fX/2 3 TI00/TO0/P20 Captur
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TMC03 TMC02 TMC01 CHAPTER 6 16-BIT
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TI00/TO0/P20 Count clock TM0 count
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CRC0 CHAPTER 6 16-BIT TIMER/EVENT C
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fX/2 3 Valid edge of TI00 TI00 pin
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Count clock TM0 count value CR00 IN
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7.1 8-Bit Timer/Event Counter Funct
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7.2 8-Bit Timer/Event Counter Confi
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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Count clock TM5n count value CR5n T
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n = 0, 1 Count clock TM5 CR5n TCE5n
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Count clock n = 0, 1 TM5n CR5n TCE5
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8.1 Watch Timer Functions The watch
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8.3 Register to Control Watch Timer
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Count clock fW/2 9 Watch timer inte
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9.1 Watchdog Timer Functions The wa
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9.2 Watchdog Timer Configuration CH
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CHAPTER 9 WATCHDOG TIMER (2) Watchd
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9.4 Watchdog Timer Operations CHAPT
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CHAPTER 10 CLOCK OUTPUT CONTROL CIR
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Address: FF40H After reset: 00H R/W
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11.1 A/D Converter Functions CHAPTE
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CHAPTER 11 A/D CONVERTER (6) ANI0 t
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CHAPTER 11 A/D CONVERTER (2) Analog
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A/D converter operation SAR ADCR0 I
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CHAPTER 11 A/D CONVERTER 11.4.3 A/D
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CHAPTER 11 A/D CONVERTER (4) Noise
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CHAPTER 12 SERIAL INTERFACE OUTLINE
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13.1 Serial Interface (UART0) Funct
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CHAPTER 13 SERIAL INTERFACE (UART0)
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13.4 Serial Interface (UART0) Opera
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Address: FFA0H After reset: 00H R/W
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Page 203 and 204: (2) Communication operations CHAPTE
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Page 215 and 216: 14.3 Serial Interface (SIO1) Contro
Page 217 and 218: CHAPTER 14 SERIAL INTERFACE (SIO1)
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Page 233 and 234: (3) Communication operation CHAPTER
Page 245 and 246: SCK1 CHAPTER 14 SERIAL INTERFACE (S
Page 247 and 248: SCK1 SO1 SI1 BUSY CSIIF1 TRF0 CHAPT
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Page 259 and 260: 16.1 Serial Interface (SIO31) Funct
Page 265 and 266: 17.1 Interrupt Function Types CHAPT
Page 267 and 268: (A) Internal non-maskable interrupt
Page 269 and 270: 17.3 Interrupt Function Control Reg
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Page 285 and 286: CHAPTER 18 EXTERNAL DEVICE EXPANSIO
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Page 295 and 296: 19.1 Standby Function and Configura
Page 297 and 298: 19.2 Standby Function Operations 19
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20.1 Reset Function CHAPTER 20 RESE
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CHAPTER 20 RESET FUNCTION Table 20-
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CHAPTER 21 μPD78F0066 The μPD78F0
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CHAPTER 21 μPD78F0066 21.2 Interna
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CHAPTER 21 μPD78F0066 21.3.2 Flash
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CHAPTER 22 INSTRUCTION SET This cha
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CHAPTER 22 INSTRUCTION SET 22.1.2 D
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Instruction Group 16-bit data trans
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Instruction Group 8-bit operation C
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Second O
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CHAPTER 22 INSTRUCTION SET (4) Call
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APPENDIX A DEVELOPMENT TOOLS The fo
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(2) When using the in-circuit emula
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APPENDIX A DEVELOPMENT TOOLS Remark
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A.3.1 Hardware (2/2) (2) When using
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A.3.2 Software (2/2) ID78K0-NS Inte
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APPENDIX A DEVELOPMENT TOOLS Conver
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APPENDIX B EMBEDDED SOFTWARE For ef
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Real-Time OS (2/2) APPENDIX B EMBED
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APPENDIX C REGISTER INDEX C.1 Regis
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16-bit timer/counter 0 (TM0) … 10
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[P] P0: Port 0 … 73 P2: Port 2
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