uPD780065 Subseries PUM - Renesas Electronics

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Symbol 226 CHAPTER 14 SERIAL INTERFACE (SIO1) (b) Automatic data transmit/receive control register (ADTC0) ADTC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC0 to 00H. Address: FF69H After reset: 00H R/WNote 1 7 6 5 4 3 2 1 0 ADTC0 RE0 ARLD0 ERCE0 ERR0 TRF0 STRB0 BUSY10BUSY00 R/W BUSY10BUSY00 Busy input control 0 × Note 2 Not using busy input 1 0 Busy input enable (active high) 1 1 Busy input enable (active low) R/W STRB0 0 1 R TRF0 Preliminary User’s Manual U13420EJ2V0UM00 0 1 R ERR0 0 1 R/W ERCE0 0 1 R/W ARLD0 0 1 R/W RE0 0 1 Strobe output control Note 3 Strobe output disable Strobe output enable Status of automatic transmit/receive functionNote 4 Detection of termination of automatic transmission/ reception (This bit is set to 0 upon suspension of automatic transmission/reception or when ARLD0 = 0.) During automatic transmission/reception (This bit is set to 1 when data is written to SIO1.) Error detection of automatic transmit/receive function No error (This bit is set to 0 when data is written to SIO1) Error occurred Error check control of automatic transmit/receive function Error check disable Error check enable (only when BUSY10 = 1) Operation mode selection of automatic transmit/ receive function Single operating mode Repetitive operating mode Receive control of automatic transmit/receive function Note 5 Receive disable Receive enable
CHAPTER 14 SERIAL INTERFACE (SIO1) Notes 1. Bits 3 and 4 (TRF0 and ERR0) are read-only bits. 2. When BUSY10 is reset to 0, P81 (CMOS I/O) is used even when bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) is set to 1. 3. When STRB0 is reset to 0, P80 (CMOS I/O) is used even when bit 7 (CSIE10) of CSIM1 is set to 1. 4. When an interrupt is acknowledged, interrupt request flag CSIIF1 is cleared. Therefore, use TRF0, instead of CSIIF1, to identify the completion of automatic transmission/reception. 5. When RE0 is reset to 0, P84 (CMOS I/O) is used even when bit 7 (CSIE10) of CSIM1 is set to 1. Caution When an external clock input is selected with CSIM1 bits 1, 0 (SCL101, SCL100) are set to 0, set ADTC0 bits 2, 1 (STRB0, BUSY10) to 0, 0. (when an external clock is input, the hand-shake control cannot be performed). Remark ×: don’t care Preliminary User’s Manual U13420EJ2V0UM00 227
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To our customers, Old Company Name
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Preliminary User’s Manual μPD780
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NOTES FOR CMOS DEVICES 1 PRECAUTION
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NEC Electronics Inc. (U.S.) Santa C
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INTRODUCTION Readers This manual ha
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• Related documents for embedded
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CONTENTS CHAPTER 1 OUTLINE ........
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5.5 Clock Generator Operations ....
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CHAPTER 15 SERIAL INTERFACE (SIO30)
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LIST OF FIGURES (1/5) Figure No. Ti
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LIST OF TABLES (1/2) Table No. Titl
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1.1 Features • Internal Memory CH
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1.4 Pin Configuration (Top View)
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1.5 78K/0 Series Lineup CHAPTER 1 O
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1.6 Block Diagram TI00/TO0/P20 TI01
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2.1 Pin Functions (1) Port Pins (1/
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(2) Non-port Pins (2/2) CHAPTER 2 P
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CHAPTER 2 PIN FUNCTION 2.2.3 P30 to
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CHAPTER 2 PIN FUNCTION 2.2.8 P80 to
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CHAPTER 2 PIN FUNCTION 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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CHAPTER 3 CPU ARCHITECTURE 3.1.1 In
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FEE0H
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CHAPTER 3 CPU ARCHITECTURE (a) Inte
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CHAPTER 3 CPU ARCHITECTURE 3.2.2 Ge
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CHAPTER 3 CPU ARCHITECTURE Table 3-
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CHAPTER 3 CPU ARCHITECTURE Table 3-
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3.3.2 Immediate addressing CHAPTER
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3.3.4 Register addressing CHAPTER 3
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3.4.2 Register addressing CHAPTER 3
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3.4.4 Short direct addressing CHAPT
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3.4.5 Special-function register (SF
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3.4.7 Based addressing CHAPTER 3 CP
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4.1 Port Functions CHAPTER 4 PORT F
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4.2 Port Configuration A port consi
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CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
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Internal bus WRPU RD WRPORT WRPM PU
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CHAPTER 4 PORT FUNCTIONS Figure 4-1
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CHAPTER 4 PORT FUNCTIONS Figure 4-1
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5.1 Clock Generator Functions CHAPT
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5.3 Clock Generator Control Registe
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CHAPTER 5 CLOCK GENERATOR The faste
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CHAPTER 5 CLOCK GENERATOR Cautions
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CHAPTER 5 CLOCK GENERATOR 5.4.3 Sca
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CHAPTER 5 CLOCK GENERATOR 5.5.1 Mai
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Set Value before Switchover CHAPTER
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CHAPTER 6 16-BIT TIMER/EVENT COUNTE
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TI01/P21 fX/2 3 TI00/TO0/P20 Captur
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TMC03 TMC02 TMC01 CHAPTER 6 16-BIT
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TI00/TO0/P20 Count clock TM0 count
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CRC0 CHAPTER 6 16-BIT TIMER/EVENT C
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fX/2 3 Valid edge of TI00 TI00 pin
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Count clock TM0 count value CR00 IN
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7.1 8-Bit Timer/Event Counter Funct
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7.2 8-Bit Timer/Event Counter Confi
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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Count clock TM5n count value CR5n T
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n = 0, 1 Count clock TM5 CR5n TCE5n
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Count clock n = 0, 1 TM5n CR5n TCE5
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8.1 Watch Timer Functions The watch
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8.3 Register to Control Watch Timer
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Count clock fW/2 9 Watch timer inte
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9.1 Watchdog Timer Functions The wa
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9.2 Watchdog Timer Configuration CH
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CHAPTER 9 WATCHDOG TIMER (2) Watchd
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9.4 Watchdog Timer Operations CHAPT
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CHAPTER 10 CLOCK OUTPUT CONTROL CIR
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Address: FF40H After reset: 00H R/W
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11.1 A/D Converter Functions CHAPTE
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Page 179 and 180: CHAPTER 11 A/D CONVERTER (2) Analog
Page 181 and 182: A/D converter operation SAR ADCR0 I
Page 183 and 184: CHAPTER 11 A/D CONVERTER 11.4.3 A/D
Page 185 and 186: CHAPTER 11 A/D CONVERTER (4) Noise
Page 187 and 188: CHAPTER 12 SERIAL INTERFACE OUTLINE
Page 189 and 190: 13.1 Serial Interface (UART0) Funct
Page 191 and 192: CHAPTER 13 SERIAL INTERFACE (UART0)
Page 195 and 196: 13.4 Serial Interface (UART0) Opera
Page 197 and 198: Address: FFA0H After reset: 00H R/W
Page 203 and 204: (2) Communication operations CHAPTE
Page 211 and 212: 14.1 Serial Interface (SIO1) Functi
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Page 217 and 218: CHAPTER 14 SERIAL INTERFACE (SIO1)
Page 227: Symbol Address: FF68H After reset:
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Page 233 and 234: (3) Communication operation CHAPTER
Page 245 and 246: SCK1 CHAPTER 14 SERIAL INTERFACE (S
Page 247 and 248: SCK1 SO1 SI1 BUSY CSIIF1 TRF0 CHAPT
Page 253 and 254: 15.1 Serial Interface (SIO30) Funct
Page 259 and 260: 16.1 Serial Interface (SIO31) Funct
Page 265 and 266: 17.1 Interrupt Function Types CHAPT
Page 267 and 268: (A) Internal non-maskable interrupt
Page 269 and 270: 17.3 Interrupt Function Control Reg
Page 271 and 272: CHAPTER 17 INTERRUPT FUNCTIONS (2)
Page 273 and 274: CHAPTER 17 INTERRUPT FUNCTIONS (4)
Page 275 and 276: 17.4 Interrupt Servicing Operations
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CHAPTER 17 INTERRUPT FUNCTIONS Figu
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CHAPTER 17 INTERRUPT FUNCTIONS 17.4
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CHAPTER 17 INTERRUPT FUNCTIONS Figu
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CHAPTER 18 EXTERNAL DEVICE EXPANSIO
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ASTB RD AD0 to AD7 A8 to A15 ASTB R
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ASTB RD WR AD0 to AD7 A8 to A15 AST
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19.1 Standby Function and Configura
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19.2 Standby Function Operations 19
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CHAPTER 19 STANDBY FUNCTION (c) Cle
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CHAPTER 19 STANDBY FUNCTION (2) STO
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20.1 Reset Function CHAPTER 20 RESE
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CHAPTER 20 RESET FUNCTION Table 20-
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CHAPTER 21 μPD78F0066 The μPD78F0
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CHAPTER 21 μPD78F0066 21.2 Interna
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CHAPTER 21 μPD78F0066 21.3.2 Flash
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CHAPTER 22 INSTRUCTION SET This cha
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CHAPTER 22 INSTRUCTION SET 22.1.2 D
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Instruction Group 16-bit data trans
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Instruction Group 8-bit operation C
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Second O
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CHAPTER 22 INSTRUCTION SET (4) Call
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APPENDIX A DEVELOPMENT TOOLS The fo
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(2) When using the in-circuit emula
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APPENDIX A DEVELOPMENT TOOLS Remark
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A.3.1 Hardware (2/2) (2) When using
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A.3.2 Software (2/2) ID78K0-NS Inte
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APPENDIX A DEVELOPMENT TOOLS Conver
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APPENDIX B EMBEDDED SOFTWARE For ef
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Real-Time OS (2/2) APPENDIX B EMBED
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APPENDIX C REGISTER INDEX C.1 Regis
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16-bit timer/counter 0 (TM0) … 10
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[P] P0: Port 0 … 73 P2: Port 2
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