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uPD780065 Subseries PUM - Renesas Electronics

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198<br />

CHAPTER 13 SERIAL INTERFACE (UART0)<br />

The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system<br />

clock.<br />

• Transmit/receive clock generation for baud rate by using main system clock<br />

The main system clock is divided to generate the transmit/receive clock. The baud rate generated from<br />

the main system clock is determined according to the following formula.<br />

[Baud rate] =<br />

fX<br />

2 n+1 (k + 16)<br />

[Hz]<br />

fX: Main system clock oscillation frequency<br />

n: Value set via TPS00 to TPS02 (0 ≤ n ≤ 7)<br />

For details, see Table 13-2.<br />

k: Value set via MDL00 to MDL03 (0 ≤ k ≤ 14)<br />

Table 13-2 shows the relationship between the 5-bit counter’s source clock assigned to bits 4 to 6 (TPS00<br />

to TPS02) of BRGC0 and the “n” value in the above formula.<br />

Table 13-2. Relationship between 5-Bit Counter’s Source Clock and “n” Value<br />

TPS02 TPS01 TPS00 5-Bit Counter’s Source Clock Selected n<br />

0 0 0 P71/ASCK0 0<br />

0 0 1 fX/2 1<br />

0 1 0 fX/2 2 2<br />

0 1 1 fX/2 3 3<br />

1 0 0 fX/2 4 4<br />

1 0 1 fX/2 5 5<br />

1 1 0 fX/2 6 6<br />

1 1 1 fX/2 7 7<br />

Remark fX: Main system clock oscillation frequency<br />

Preliminary User’s Manual U13420EJ2V0UM00

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