uPD780065 Subseries PUM - Renesas Electronics
uPD780065 Subseries PUM - Renesas Electronics
uPD780065 Subseries PUM - Renesas Electronics
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LIST OF FIGURES (2/5)<br />
Figure No. Title Page<br />
6-9 Timing of Interval Timer Operation .................................................................................................... 115<br />
6-10 Control Register Settings for PPG Output Operation ....................................................................... 116<br />
6-11 Control Register Settings for Pulse Width Measurement with Free-Running Counter<br />
and One Capture Register ................................................................................................................ 117<br />
6-12 Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................ 118<br />
6-13 Timing of Pulse Width Measurement Operation by Free-Running Counter<br />
and One Capture Register (with Both Edges Specified) ................................................................... 118<br />
6-14 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ........ 119<br />
6-15 Capture Operation with Rising Edge Specified ................................................................................. 120<br />
6-16 Timing of Pulse Width Measurement Operation with Free-Running Counter<br />
(with Both Edges Specified) .............................................................................................................. 120<br />
6-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter<br />
and Two Capture Registers .............................................................................................................. 121<br />
6-18 Timing of Pulse Width Measurement Operation by Free-Running Counter<br />
and Two Capture Registers (with Rising Edge Specified) ................................................................ 122<br />
6-19 Control Register Settings for Pulse Width Measurement by Means of Restart ................................ 123<br />
6-20 Timing of Pulse Width Measurement Operation by Means of Restart<br />
(with Rising Edge Specified) ............................................................................................................. 123<br />
6-21 Control Register Settings in External Event Counter Mode .............................................................. 124<br />
6-22 External Event Counter Configuration Diagram ................................................................................ 125<br />
6-23 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 125<br />
6-24 Control Register Settings in Square-Wave Output Mode ................................................................. 126<br />
6-25 Square-Wave Output Operation Timing ............................................................................................ 127<br />
6-26 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ................ 128<br />
6-27 Timing of One-Shot Pulse Output Operation Using Software Trigger ............................................... 129<br />
6-28 16-Bit Timer/Counter 0 (TM0) Start Timing ....................................................................................... 130<br />
6-29 Timings after Change of Compare Register during Timer Count Operation ..................................... 130<br />
6-30 Capture Register Data Retention Timing .......................................................................................... 131<br />
6-31 Operation Timing of OVF0 Flag ........................................................................................................ 132<br />
7-1 8-Bit Timer/Event Counter 50 Block Diagram ................................................................................... 136<br />
7-2 8-Bit Timer/Event Counter 51 Block Diagram ................................................................................... 136<br />
7-3 Format of Timer Clock Select Register 50 (TCL50) .......................................................................... 138<br />
7-4 Format of Timer Clock Select Register 51 (TCL51) .......................................................................... 139<br />
7-5 Format of 8-Bit Timer Mode Control Register 5n (TMC5n) ............................................................... 140<br />
7-6 Format of Port Mode Register 2 (PM2) ............................................................................................. 141<br />
7-7 Interval Timer Operation Timings ...................................................................................................... 143<br />
7-8 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 146<br />
7-9 Square-Wave Output Operation Timing ............................................................................................ 147<br />
7-10 PWM Output Operation Timing ......................................................................................................... 149<br />
7-11 Timing of Operation by Change of CR5n .......................................................................................... 150<br />
7-12 16-Bit Resolution Cascade Connection Mode .................................................................................. 152<br />
7-13 8-Bit Counter Start Timing ................................................................................................................ 152<br />
7-14 Timing after Compare Register Transition during Timer Count Operation ........................................ 153<br />
18 Preliminary User’s Manual U13420EJ2V0UM00
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