uPD780065 Subseries PUM - Renesas Electronics

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[MEMO] 186 Preliminary User’s Manual U13420EJ2V0UM00
13.1 Serial Interface (UART0) Functions CHAPTER 13 SERIAL INTERFACE (UART0) The serial interface (UART0) has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. In addition, a baud rate can also be defined by dividing clocks input to the ASCK0 pin. The UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). For details, see 13.4.2 Asynchronous serial interface (UART) mode. (3) Infrared data transfer mode For details, see 13.4.3 Infrared data transfer mode. RxD0/P73 TxD0/P72 Figure 13-1 shows a block diagram of the serial interface (UART0) macro. Receive buffer register (RXB0) Receive shift register (RX0) Receive controller (parity check) Figure 13-1. Serial Interface (UART0) Block Diagram PE0 FE0 OVE0 INTSR0 Asynchronous serial interface status register (ASIS0) Internal bus INTSER0 Transmit shift register (TXS0) Transmit controller (parity addition) INTST0 Preliminary User’s Manual U13420EJ2V0UM00 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0 Baud rate generator Asynchronous serial interface mode register (ASIM0) ASCK0/P71 fX/2 to fX/2 7 187
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To our customers, Old Company Name
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Preliminary User’s Manual μPD780
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NOTES FOR CMOS DEVICES 1 PRECAUTION
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NEC Electronics Inc. (U.S.) Santa C
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INTRODUCTION Readers This manual ha
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• Related documents for embedded
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CONTENTS CHAPTER 1 OUTLINE ........
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5.5 Clock Generator Operations ....
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CHAPTER 15 SERIAL INTERFACE (SIO30)
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LIST OF FIGURES (1/5) Figure No. Ti
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LIST OF TABLES (1/2) Table No. Titl
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1.1 Features • Internal Memory CH
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1.4 Pin Configuration (Top View)
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1.5 78K/0 Series Lineup CHAPTER 1 O
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1.6 Block Diagram TI00/TO0/P20 TI01
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2.1 Pin Functions (1) Port Pins (1/
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(2) Non-port Pins (2/2) CHAPTER 2 P
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CHAPTER 2 PIN FUNCTION 2.2.3 P30 to
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CHAPTER 2 PIN FUNCTION 2.2.8 P80 to
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CHAPTER 2 PIN FUNCTION 2.3 Pin I/O
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3.1 Memory Space CHAPTER 3 CPU ARCH
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CHAPTER 3 CPU ARCHITECTURE 3.1.1 In
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CHAPTER 3 CPU ARCHITECTURE 3.1.2 In
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FFFFH FF20H FF1FH FF00H FEFFH FEE0H
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CHAPTER 3 CPU ARCHITECTURE (a) Inte
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CHAPTER 3 CPU ARCHITECTURE 3.2.2 Ge
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CHAPTER 3 CPU ARCHITECTURE Table 3-
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CHAPTER 3 CPU ARCHITECTURE Table 3-
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3.3.2 Immediate addressing CHAPTER
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3.3.4 Register addressing CHAPTER 3
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3.4.2 Register addressing CHAPTER 3
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3.4.4 Short direct addressing CHAPT
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3.4.5 Special-function register (SF
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3.4.7 Based addressing CHAPTER 3 CP
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4.1 Port Functions CHAPTER 4 PORT F
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4.2 Port Configuration A port consi
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CHAPTER 4 PORT FUNCTIONS 4.2.2 Port
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Internal bus WRPU RD WRPORT WRPM PU
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CHAPTER 4 PORT FUNCTIONS Figure 4-1
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CHAPTER 4 PORT FUNCTIONS Figure 4-1
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5.1 Clock Generator Functions CHAPT
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5.3 Clock Generator Control Registe
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CHAPTER 5 CLOCK GENERATOR The faste
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CHAPTER 5 CLOCK GENERATOR Cautions
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CHAPTER 5 CLOCK GENERATOR 5.4.3 Sca
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CHAPTER 5 CLOCK GENERATOR 5.5.1 Mai
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Set Value before Switchover CHAPTER
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CHAPTER 6 16-BIT TIMER/EVENT COUNTE
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TI01/P21 fX/2 3 TI00/TO0/P20 Captur
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TMC03 TMC02 TMC01 CHAPTER 6 16-BIT
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TI00/TO0/P20 Count clock TM0 count
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CRC0 CHAPTER 6 16-BIT TIMER/EVENT C
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fX/2 3 Valid edge of TI00 TI00 pin
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Count clock TM0 count value CR00 IN
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Page 137 and 138: 7.1 8-Bit Timer/Event Counter Funct
Page 139 and 140: 7.2 8-Bit Timer/Event Counter Confi
Page 141 and 142: CHAPTER 7 8-BIT TIMER/EVENT COUNTER
Page 145 and 146: Count clock TM5n count value CR5n T
Page 147 and 148: n = 0, 1 Count clock TM5 CR5n TCE5n
Page 151 and 152: Count clock n = 0, 1 TM5n CR5n TCE5
Page 157 and 158: 8.1 Watch Timer Functions The watch
Page 159 and 160: 8.3 Register to Control Watch Timer
Page 161 and 162: Count clock fW/2 9 Watch timer inte
Page 163 and 164: 9.1 Watchdog Timer Functions The wa
Page 165 and 166: 9.2 Watchdog Timer Configuration CH
Page 167 and 168: CHAPTER 9 WATCHDOG TIMER (2) Watchd
Page 169 and 170: 9.4 Watchdog Timer Operations CHAPT
Page 171 and 172: CHAPTER 10 CLOCK OUTPUT CONTROL CIR
Page 173 and 174: Address: FF40H After reset: 00H R/W
Page 175 and 176: 11.1 A/D Converter Functions CHAPTE
Page 177 and 178: CHAPTER 11 A/D CONVERTER (6) ANI0 t
Page 179 and 180: CHAPTER 11 A/D CONVERTER (2) Analog
Page 181 and 182: A/D converter operation SAR ADCR0 I
Page 183 and 184: CHAPTER 11 A/D CONVERTER 11.4.3 A/D
Page 185 and 186: CHAPTER 11 A/D CONVERTER (4) Noise
Page 187: CHAPTER 12 SERIAL INTERFACE OUTLINE
Page 191 and 192: CHAPTER 13 SERIAL INTERFACE (UART0)
Page 195 and 196: 13.4 Serial Interface (UART0) Opera
Page 197 and 198: Address: FFA0H After reset: 00H R/W
Page 203 and 204: (2) Communication operations CHAPTE
Page 211 and 212: 14.1 Serial Interface (SIO1) Functi
Page 213 and 214: Figure 14-1. Block Diagram of Seria
Page 215 and 216: 14.3 Serial Interface (SIO1) Contro
Page 217 and 218: CHAPTER 14 SERIAL INTERFACE (SIO1)
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Page 233 and 234: (3) Communication operation CHAPTER
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SCK1 CHAPTER 14 SERIAL INTERFACE (S
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SCK1 SO1 SI1 BUSY CSIIF1 TRF0 CHAPT
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15.1 Serial Interface (SIO30) Funct
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16.1 Serial Interface (SIO31) Funct
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17.1 Interrupt Function Types CHAPT
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(A) Internal non-maskable interrupt
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17.3 Interrupt Function Control Reg
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CHAPTER 17 INTERRUPT FUNCTIONS (2)
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CHAPTER 17 INTERRUPT FUNCTIONS (4)
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17.4 Interrupt Servicing Operations
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CHAPTER 17 INTERRUPT FUNCTIONS Figu
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CHAPTER 17 INTERRUPT FUNCTIONS 17.4
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CHAPTER 18 EXTERNAL DEVICE EXPANSIO
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ASTB RD AD0 to AD7 A8 to A15 ASTB R
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ASTB RD WR AD0 to AD7 A8 to A15 AST
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19.1 Standby Function and Configura
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19.2 Standby Function Operations 19
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CHAPTER 19 STANDBY FUNCTION (c) Cle
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CHAPTER 19 STANDBY FUNCTION (2) STO
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20.1 Reset Function CHAPTER 20 RESE
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CHAPTER 20 RESET FUNCTION Table 20-
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CHAPTER 21 μPD78F0066 The μPD78F0
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CHAPTER 21 μPD78F0066 21.2 Interna
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CHAPTER 21 μPD78F0066 21.3.2 Flash
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CHAPTER 22 INSTRUCTION SET This cha
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CHAPTER 22 INSTRUCTION SET 22.1.2 D
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Instruction Group 16-bit data trans
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Instruction Group 8-bit operation C
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Instruct
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CHAPTER 22 INSTRUCTION SET Second O
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CHAPTER 22 INSTRUCTION SET (4) Call
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APPENDIX A DEVELOPMENT TOOLS The fo
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(2) When using the in-circuit emula
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APPENDIX A DEVELOPMENT TOOLS Remark
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A.3.1 Hardware (2/2) (2) When using
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A.3.2 Software (2/2) ID78K0-NS Inte
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APPENDIX A DEVELOPMENT TOOLS Conver
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APPENDIX B EMBEDDED SOFTWARE For ef
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Real-Time OS (2/2) APPENDIX B EMBED
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APPENDIX C REGISTER INDEX C.1 Regis
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16-bit timer/counter 0 (TM0) … 10
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[P] P0: Port 0 … 73 P2: Port 2
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