uPD780065 Subseries PUM - Renesas Electronics

9.4 Watchdog Timer Operations
CHAPTER 9 WATCHDOG TIMER
9.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to
detect any runaway.
The runaway detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock
select register (WDCS).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within
the set runaway time interval. The watchdog timer can be cleared and counting is started by setting RUN to 1. If
RUN is not set to 1 and the runaway detection time is exceeded, system reset or a non-maskable interrupt request
is generated according to WDTM bit 3 (WDTM3) value.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual runaway detection time may be shorter than the set time by a maximum of
0.5%.
2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
stopped.
Table 9-4. Watchdog Timer Runaway Detection Time
Runaway Detection Time
2 12 × 1/fX (489 μs)
2 13 × 1/fX (978 μs)
2 14 × 1/fX (1.96 ms)
2 15 × 1/fX (3.91 ms)
2 16 × 1/fX (7.82 ms)
2 17 × 1/fX (15.6 ms)
2 18 × 1/fX (31.3 ms)
2 20 × 1/fX (125 ms)
Remarks 1. fX: Main system clock oscillation frequency
2. Figures in parentheses are for operation with fX = 8.38 MHz.
Preliminary User’s Manual U13420EJ2V0UM00
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